Designing High-Performance Fuzzy Controllers Combining IP Cores and Soft Processors
Figure 7
The FLC has two inputs: Error and Change of error, and one output. The output provides a value of increment/decrement to be use by the integral part of the PD+I controller. The first scale [0, 255] are the real MFs bit values definition in the FLC. The second scale [−80, 80] and [−100, 100] are the operation values for this application. The scale conversion is achieved by the ARM processor.
