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Advances in Mechanical Engineering
Volume 2014 (2014), Article ID 203793, 18 pages
http://dx.doi.org/10.1155/2014/203793
Research Article

Study on the Control Algorithm of Two-Stage DC-DC Converter for Electric Vehicles

1Institution of Pattern Recognition and Application, College of Automation, Chongqing University of Posts and Telecommunications, Chongqing 400065, China
2Department of Mechanical Engineering, INHA University, Incheon 402751, Republic of Korea

Received 11 September 2013; Accepted 2 November 2013; Published 21 January 2014

Academic Editor: Xiaosong Hu

Copyright © 2014 Changhao Piao et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Abstract

The fast response, high efficiency, and good reliability are very important characteristics to electric vehicles (EVs) dc/dc converters. Two-stage dc-dc converter is a kind of dc-dc topologies that can offer those characteristics to EVs. Presently, nonlinear control is an active area of research in the field of the control algorithm of dc-dc converters. However, very few papers research on two-stage converter for EVs. In this paper, a fixed switching frequency sliding mode (FSFSM) controller and double-integral sliding mode (DISM) controller for two-stage dc-dc converter are proposed. And a conventional linear control (lag) is chosen as the comparison. The performances of the proposed FSFSM controller are compared with those obtained by the lag controller. In consequence, the satisfactory simulation and experiment results show that the FSFSM controller is capable of offering good large-signal operations with fast dynamical responses to the converter. At last, some other simulation results are presented to prove that the DISM controller is a promising method for the converter to eliminate the steady-state error.

1. Introduction

Depleting fossil fuel supply and increasing regulations on greenhouse continue to pressure the automotive industry to transition toward more sustainable energy sources [1]. Due to numerous advantages in energy conservation and environmental protection, electrified vehicles which include battery electric vehicles (BEVs), hybrid electric vehicles (HEVs), and plug-in hybrid electric vehicles (PHEVs) have been actively studied and developed and are widely viewed as an important transition towards sustainable transportation [13]. The development of EVs power electronics system control, composed of dc-ac inverters and dc-dc converters, appeals to large numbers of researchers in the modern industry. A dc-ac inverter supplies the high power electric vehicle motors torques of the propulsion system and utility loads, whereas a dc-dc converter supplies conventional low-power and low-voltage loads [4]. As an important component of EVs, dc-dc converter is added to make the power battery and inverter work harmoniously. Although a lot of methods are used to provide monitoring, diagnosis, and control functions to enhance the operations of battery packs [13, 5, 6], it is necessary to study the dc-dc converter to ensure its stability and reliability. Two-stage dc-dc converter topologies have recently begun to receive interest in high input voltage, low voltage/high current output dc-dc conversion [710]. Generally, the two-stage topologies compose of a buck converter and an isolated one. As the first stage, the buck converter is used to regulate the output. And the isolated one, including forward, push-pull, half-bridge and full bridge, works as the second stage to operate with 50% duty ratio to step down the voltage. In this paper, a buck + half bridge (Figure 1) topology is chosen.

203793.fig.001
Figure 1: Two-stage dc-dc converter.

Because it is a fourth-order, nonlinear, and time-varying system, the control of two-stage converter is becoming a challenging problem. Current control methods for two-stage converters all rely on conventional linear voltage or current controller [711]. Although the implementation is simple, these controllers cannot provide good regulation for the converters when operated at a point that deviates too far away from the desired condition. At the same time, these controllers are very sensitive to the variation of circuit parameters, change in working state, and the variations of load and line voltage. The proposed nonlinear controller can perform better against these problems as dc-dc converters are inherently variable structure systems (VSSs) [12]. The sliding mode control (SMC) utilizes a high-speed switching control law to drive the nonlinear state trajectory onto specified surface in the state space and to maintain it on this surface for all subsequent times [13]. Application of SMC at variety of sliding surfaces for dc-dc converters has been well addressed in the past [14, 15]. All these SM controllers offer many merits over the linear controllers.

In this paper, a fixed switching frequency sliding mode (FSFSM) controller and double-integral sliding mode (DISM) controller for two-stage dc-dc converter is proposed. And a conventional linear control (lag) controller is chosen as the comparison. Owing to the time-varying switched mode operation, the dynamic performance of the two-stage converter becomes high order and nonlinear. In order to design the FSFSM controller, DISM controller, and lag controller, the state-space averaging model and averaged switch model are established, respectively. The modeling of FSFSM controller and DISM controller for two-stage converter are proposed in continuous conduction mode (CCM). The controllers are implemented via PWM form, which offers good large-signal control performances with fast dynamical response to the two-stage converter.

Then the three conditions of sliding mode control, namely, hitting, existence, and stability conditions, are analyzed as well as the bode diagram of the transfer function of the converter. Further, the corresponding controllers are designed. The performances of the proposed FSFSM controller are compared with those obtained by the lag controller. In consequence, the satisfactory results show that the FSFSM controller is capable of offering good large-signal operations with fast dynamical responses to the converter. At last, some other simulation results are presented to prove that the DISM controller is a promising method for the converter to eliminate the steady-state error.

2. Modeling of Two-Stage Converter

The basic configuration of the two-state converter, which consists of an input inductor , a power switch , two energy transfer capacitors , an output inductor , and capacitor , is shown in Figure 1. Thanks to the two switches both get a complementary 50% duty ratio; the half bridge topology is replaced by an equivalent circuit, as illustrated in Figure 2.

203793.fig.002
Figure 2: Simplified two-stage converter.

In Figure 2, the output inductor , capacitor , and the resistor are converted to the primary winding of the transformer by the following, where denotes the turn ration of the transformer:

2.1. Modeling for FSFSM Controller and DISM Controller

In this part, it is assumed that all the components are ideal and the two-stage converter operates in CCM. In order to analyse the operation of the converter, the circuit is divided into two states, namely, the switch-ON and the switch-OFF.

As Figure 3 showed, when the switch is on, the capacitor is charged by supply voltage in the short duration of time period. The output capacitor provides energy to the output load. When the switch is off, the diode D1 is conductive. The state-space equation can be described as (2) and (3), respectively,

203793.fig.003
Figure 3: Simplified two-stage converter.

Using the state-space averaging method, the whole switching conditions can be derived from (4), where is the state of the switch. When the switch is on and off, and 0, respectively. In order to get the state variables which can be used directly in the control, the substitution of (1) into (4) and the state-space model of the two-stage dc-dc converter can be expressed as

2.2. Modeling for Lag Controller

In order to get the transfer function of the lag controller, it is necessary to simplify switch network 1. It is found that switch network 1 is a buck switch network. Here, we use its averaged switch model directly. The detailed processes are expressed in [16]. In this way, the circuit shown in Figure 2 is converted into that in Figure 4.

203793.fig.004
Figure 4: Averaged switch model of the two-stage converter.

In Figure 4, , , , and denote duty cycle, duty cycle variation, input voltage variation, and output voltage variation, respectively. In order to get the control-to-output transfer function of the converter, we let , namely, it is short-circuited. Hence, the primary winding of the ac and dc transformer in switch network 1 is short-circuited and ineffective. Using the Laplace transforms for the circuit, the new structure is shown in Figure 5.

203793.fig.005
Figure 5: The final simplified two-stage converter.

It is easy to obtain the control-to-output transfer function of the converter from Figure 5:

Equation (6) is simplified as where

3. Design of the Controller for Two-Stage Converter

In order to design the controller for the converter, we have used different methods to model two models for the two-stage converter. One for FSFSM controller and DISM controller and the other for lag controller.

3.1. Design of the FSFSM Controller

In an ideal sliding mode control, all the state variables are sensed and added to the sliding surface to improve the dynamic characteristic, but this also increase complexity of application. As a tradeoff, only two state variables of the two-state dc-dc converter are chosen to be controller parameters. In the case of SM controller, the control variable may be expressed in the following form: where and denote the current of inductor and the output voltage, respectively,

The authors of [17] use the state variables and the integral of the state-variable errors to form the sliding surface. In this way, the sliding surface of the two-stage converter is expressed as where and are positive controller coefficients; and denote the feedback network ratio and the reference output voltage. The use of integral term in (11) is to reduce the steady-state errors.

3.1.1. Dynamic Model of Proposed Controller and Its Equivalent Control

By using (10) and (11), we get

The equivalent control signal of the proposed FSFSM controller when applied to the converter is obtained by solving the . The equivalent control signal is found in (12) and expressed as (13). It is noted that the state variable and appear in (13). These variables are essential in feedback controller design:

The proposed SM controller, which operates at fixed-frequency, is implemented through a pulse-width modulator by adopting a set of control laws derived by using indirect SM control technique [18]. The equation of the control laws comprises a control signal and a fixed frequency ramp signal , which maintains the constant frequency of the operation. The controller’s structure is illustrated in Figure 6. The control equation can be expressed as where and . The factor of has been introduced to scale down the equation to conform to the chip level voltage standard and the assumption . With this, the equivalent control signal in (12) can be expressed as where is continuous and .

203793.fig.006
Figure 6: Controller structure of the FSFSM controller applied to two-stage converter.
3.1.2. Existence Condition

A system with the description is said to exhibit SM property when all the required conditions, namely, existence condition, hitting condition, and stability condition, are met [19]. Satisfaction of the existence condition ensures that the state trajectory at locations near the sliding surface will always be directed towards the sliding surface. Mathematically, the existence condition can be represented as when , , when , ,

Assuming the controller is designed with a static sliding surface to meet the existence condition for steady-state operations (equilibrium point), then (17) and (18) can be simplified as where the , , , and denote the maximum input voltage, the maximum voltage of energy transfer capacitor, the maximum current of output capacitor, and the maximum output voltage, respectively.

3.1.3. Hitting Condition

This condition ensures that the system representing point can eventually reach the sliding surface starting from any point in the state space. Mathematically, it can be represented as

For the proposed FSFSM controller, the hitting condition has been satisfied by the appropriate choice of the switching function shown in the existence condition.

3.1.4. Stability Condition

Satisfaction of the stability condition ensures that the state trajectory of the system under SM operation will always reach a stable equilibrium point. For the designed FSFSMC, the stability condition can be derived by finding the ideal dynamics of the system first and then analysed on its equilibrium point [20].

Ideal sliding dynamics: the replacement of by into the original two-stage converter’s description under CCM operation converts the discontinuous system into an ideal SM continuous system as follows: Then, the substitution of the equivalent control signal (15) into (21), gives

Equilibrium point: assume that there exists a stable equilibrium point on the sliding surface on which the ideal sliding dynamics eventually settled. At this equilibrium (steady state), any change will not appear in the system’s dynamics if there is no input or loading disturbance [19], that is, Then, the state equation in (22) can be equated to where , , , and denote the output voltage, capacitor voltage, output inductor current, and load resistance at steady-state equilibrium condition, respectively.

Linearization of ideal sliding dynamics: by separating the ideal sliding mode dynamic`s equation (22) into AC and DC terms, we have where , , , and , , , denote the AC and DC terms, respectively.

Equation (25) satisfies the static equilibrium conditions, , , , , and the assumption , , and . The linearization of the ideal sliding dynamics around the equilibrium point given in (24) transforms (25) into (26). Equation (27) is obtained by rearranging (26) to the standard form: where , , , , , ; ; , and the others equal zero.

The characteristic equation of the linearised system is given by where

The application of the Routh criterion to the characteristic equation in (28) shows that the system will be stable if the following conditions are satisfied:

Thus, the rough range of the controller’s coefficients is obtained by using the Routh array criterion method at first and then fine tuning the coefficients and to get appropriate dynamic response through the three FSFSMC conditions. Then we get , , , and . Finally, the structure of SM controller is obtained and is shown in Figure 10.

3.2. Design of the Double-Integral Sliding Mode Controller

The previous section discussed the design of the FSFSM controller. Actually, the FSFSM controller is an integral sliding mode (ISM) controller in the indirect form which is expressed as (31). And its derivative and equivalent control signal are expressed as (32) and (33), respectively,

For implementation of the ISM controller, the original control law must be expressed in an alternate form. This is based on the equivalent control method, which assumes the invariance conditions in which during SM operation, and . From such an assumption, an equivalent control signal can be derived in terms of the respective state variables. Hence, the trajectory is indirectly formulated to track the desired sliding surface through the construction of the control signal . This makes it an indirect approach for ensuring SM operation. However, for the indirect ISM controller, the variables are not explicitly reflected in the control signal [19]. Hence, when steady-state errors are present in the computation, the indirect ISM controller is effective in reducing the steady-state error but ineffective in eliminating the steady-state error.

It is well known that the increased order of the controller improves the steady-state accuracy of the system but aggravates the stability problem [21]. A possible solution is to introduce an additional double-integral term of the state variables. By using an integral closed-loop to eliminate the steady-state error of the indirect integral computation, the steady-state errors of the controlled state variables can be eliminated. This is the so-called double-integral sliding mode (DISM) controller [19].

In the case of DISM controller, we define the sliding surface as the following form: where , , , and represent the desired sliding coefficients. The control variables are the current error , the voltage error , the integral of the sum of the current and the voltage errors , and the double integral of the sum of the current and the voltage errors , which are expressed as where and and denote the amplified gain of the voltage error and the feedback network ratio.

3.2.1. Dynamic Model of Proposed Controller and Its Equivalent Control

The derivative of (35) is expressed as By substituting (35) into (31), we get the sliding surface of the two-stage converter. And its derivative is shown as follows:

In the same way, the equivalent control signal is obtained by solving : Also, it is easy to get the control signal and the fixed frequency ramp signal : where , , are the fixed gain parameters in the controller. A factor of has been introduced to scale down the equation to conform to the chip level voltage standard.

3.2.2. Existence Condition

The existence condition of the sliding mode can be derived with a candidate Lyapunov function. Let this function be

Satisfaction of the existence condition ensures that the state trajectory at locations near the sliding surface will always be directed towards the sliding surface. Mathematically, the existence condition can be represented as Equation (42) can be expressed as when , , when , ,

Assuming the controller is designed with a static sliding surface to meet the existence condition for steady-state operations (equilibrium point), then (44) and (45) can be simplified as where the and denote the maximum and minimum output capacitor currents; denotes the minimum input voltage; is the output voltage of capacitor at steady state; and denote maximum and minimum steady-state current errors, respectively; and are, respectively, the maximum and minimum steady-state errors; and are, respectively, the maximum and minimum integrals of the combination of steady-state voltage and current errors.

3.2.3. Hitting Condition

The objective of the hitting condition is to ensure that regardless of the location of the initial condition, the corresponding control decision will direct the trajectory of the system to approach and eventually reach the sliding manifold. Mathematically, it can be expressed as (20). As in the previous section, the hitting condition of the proposed DISM controller has been satisfied by the appropriate choice of the switching function shown in the existence condition.

3.2.4. Stability Condition

In addition to the existence condition, the control action and sliding coefficients must be designed to comply with the stability condition. This is to ensure that in the event of operating in the sliding phase, the desired sliding manifold will always direct the trajectory toward a stable equilibrium point. Failure to achieve this will lead to the DISM system which is unstable [19]. For the designed FSFSMC, the stability condition can be derived by finding the ideal dynamics of the system first and then analyzed on its equilibrium point [20].

Ideal sliding dynamics: the replacement of u by into the original two-stage converter’s description under CCM operation converts the discontinuous system into an ideal DISM continuous system in (21). Then, the substitution of the equivalent control signal (39) into (21) gives (47):

Equilibrium point: assume that there exists a stable equilibrium point on the sliding surface on which the ideal sliding dynamics eventually settled. At this equilibrium (steady state), any change will not appear in the system’s dynamics if there is no input or loading disturbance [19], that is, Then, the state equation in (47) can be equated to where , , , and denote the output voltage, capacitor voltage, output inductor current, and load resistance at steady-state equilibrium condition, respectively.

Linearization of ideal sliding dynamics: by separating the ideal sliding dynamic’s equation (47) into AC and DC terms gives where , , , and , , , denote the AC and DC terms, respectively.

Equation (50) satisfies the static equilibrium conditions , , and the assumption , , and . The linearization of the ideal sliding dynamics around the equilibrium point given in (49) transforms (50) into (51). Equation (52) is obtained by rearranging (51) to the standard form: where and the others equal zero.

Then characteristic equation of the linearized system is given by where , , , , , and are the coefficients in the polynomial.

The application of the Routh criterion to the characteristic equation in (54) shows that the system will be stable if the following conditions are satisfied:

Then, the approximate range of the controller’s coefficients is obtained by using the Routh array criterion method at first and then fine tuning the coefficients , , , and to get appropriate dynamic response through the three conditions. Finally, we get , , , , , and . And the structure of the DISM controller is shown in Figure 11.

3.3. Design of the Lag Controller

Before designing the lag controller, it is necessary to study the characteristic of the transfer function . To introduce the specifications of the two-stage converter into (3) and (4), we get (56) and its bode diagram is shown in Figure 6:

The specifications of the two-stage converter are shown in Table 1.

tab1
Table 1: Specifications of the two-stage dc-dc converter.

From (56) and Figure 7, it is found that the control-to-output transfer function of the converter is a fourth-order system with two pairs of conjugate poles which cause resonance, and its phase shifts to −270° at the second resonance point. Analysis shows that the first resonance frequency is mainly determined by , , and , while the second resonance frequency is mainly determined by , , and . So the controller is designed to increase the second resonance frequency to achieve a higher bandwidth [11]. Using Matlab control toolbox “SISOTOOL,” the transfer function of the compensator and the compensated bode diagram are obtained and shown in (57) and Figure 9, respectively,

203793.fig.007
Figure 7: The bode diagram of transfer function .

In Figure 8, F, H, C, and G represent reference voltage, feedback-loop sensor, compensator, and transfer function of the system, respectively. Because the output voltage is 13 v, we set H = 0.25 and F = 3.25.

203793.fig.008
Figure 8: SISOTOOL of Matlab.
203793.fig.009
Figure 9: The bode diagram of the compensated open-loop transfer function.
203793.fig.0010
Figure 10: Simulation mode for two-stage converter with FSFSM controller.
203793.fig.0011
Figure 11: Simulation mode of two-stage converter with DISM controller.

By adding zero and pole to the open-loop transfer function and fine tuning, we get a satisfactory bode diagram. In the picture,  Hz and °, so they can meet the requirement. And the structure of the lag controller is shown in Figure 12.

203793.fig.0012
Figure 12: Simulation mode for two-stage converter with lag controller.

4. Simulation and Experimental Results

Using (5), (14), (40), (57), and the obtained coefficients, the simulation models for FSFSM controller, DISM controller, and lag controller are modeled by Matlab/Simulink. The three simulation models have the same dc-dc converter which is shown in Figure 13.

203793.fig.0013
Figure 13: Simulation mode of two-stage converter.
4.1. Simulation and Experiment Results of Lag Controller and FSFSM Controller

In the following part, some simulation and experiment results are given. As the emphasis of the paper, we will discuss the simulation and experiment results of FSFSM controller and lag controller in detail. As a further study, the simulation results of FSFSM controller and DISM controller will be discussed later as well. The validation of the controllers’ performance is accomplished for three different conditions, namely, startup transient, line variation, and load variation.

4.1.1. Startup Transient

Figure 14 shows the simulated start-up responses of output voltage using the lag controller and FSFSM controller. It can be seen that the setting times of lag controller and FSFSM controller are 0.02 s and 0.014 s, respectively. From Figure 15, it is clearly found that the setting times of lag controller and FSFSM controller are 0.2 s and 0.1 s, respectively. From Figures 15(a) and 15(b), it is clearly identified that the experimental results confirm the simulation results. Obviously, the FSFSM controller has a faster response than the lag controller.

203793.fig.0014
Figure 14: Simulated start-up responses of output voltage for lag controller and FSFSM controller.
fig15
Figure 15: Experimental start-up responses of the output voltage for (a) lag controller and (b) FSFSM controller.
4.1.2. Line Variation

Figure 16 shows the simulated responses of output voltage under line variation for input voltage step change from 144 v to 172.8 v (+20% line variations) at 0.05 s. In the picture, it can be found that the simulated responses of output voltage with lag controller have a voltage ripple of 2.12 v and a settling time of 0.02 s, while the designed FSFSM controller almost has negligible change under this condition. Figures 17(a) and 17(b) show the experimental responses of output voltage under line variation for input voltage step change from 144 v to 172.8 v. It can be found that the experimental responses of output voltage with lag controller have a voltage ripple of 2.2 v and a settling time of 0.23 s, whereas the output voltage using an FSFSM controller has a voltage ripple of 0.6 v and settling time of 0.13 s.

203793.fig.0016
Figure 16: Simulated responses of output voltage for lag controller and FSFSM controller for input voltage step change from 144 v to 172.8 v (+20% line variations).
fig17
Figure 17: Experimental responses of the output voltage for (a) lag controller and (b) FSFSM controller for input voltage step change from 144 v to 172.8 v (+20% line variations).

Figure 18 shows the simulated responses of output voltage with the lag controller and FSFSM controller under line variation for line step change from 144 v to 115.2 v (−20% line variations) at 0.05 s. It can be found that the simulated responses of output voltage with lag controller have a voltage ripple of 1.4 v and a settling time of 0.019 s, while the designed FSFSM controller almost has negligible change under this condition.

203793.fig.0018
Figure 18: Simulated responses of output voltage for lag controller and FSFSM controller for input voltage step change from 144 v to 115.2 v (−20% line variations).

Figures 19(a) and 19(b) show the experimental responses of output voltage under line variation for input voltage step change from 144 v to 115.2 v. It can be found that the experimental responses of output voltage with lag controller have a voltage ripple of 2.0 v and a settling time of 0.22 s, whereas the output voltage of the same converter using the designed FSFSM controller has a voltage ripple of 0.4 v and a settling time of 0.12 s.

fig19
Figure 19: Experimental responses of the output voltage for (a) lag controller and (b) FSFSM controller for input voltage step change from 144 v to 115.2 v (−20% line variations).

From Figure 17 to Figure 19, it is clearly identified that the experimental results confirm the simulation results under line variations for the designed FSFSM controller except for little variation in experimental output voltage response. From Figure 16 to Figure 19, it is clearly found that the simulated and experimental responses of the designed FSFSM controller showed better performance in comparison with lag controller under line variation.

4.1.3. Load Variation

Figure 20 depicts the simulated responses of output voltage of the two-stage converter, which are performed with lag controller and FSFSM controller, respectively, for load step change from 20 mΩ to 24 mΩ (+20% load variations) at 0.05 s. From Figure 20, it can be found that the simulated results of output voltage using a lag controller have a voltage ripple of 2.5 v and a settling time of 0.02 s, whereas the output voltage with the designed FSFSM controller has a voltage ripple of 2.2 v and a settling time of 0.003 s. Comparing both figures, it is clearly found that the FSFSM controller has a lower voltage ripple and quicker settling time. Figures 21(a) and 21(b) show the experimental results of output voltage under the same condition. It can be found that the experimental responses of output voltage with lag controller have a voltage ripple of 2.2 v and a settling time of 0.2 s, whereas the output voltage using the designed FSFSM controller has a voltage ripple of 1.8 v and a settling time of 0.14 s.

203793.fig.0020
Figure 20: Simulated responses of output voltage for lag controller and FSFSM controller for input voltage step change from 20 mΩ to 24 mΩ (+20% load variations).
fig21
Figure 21: Experimental responses of output voltage for (a) lag controller and (b) FSFSM controller for load step change from 20 mΩ to 24 mΩ (+20% load variations).

Figure 22 depicts the simulated results of output voltage under load variation for load step change from 20 mΩ to 16 mΩ (−20% load variations) at 0.05 s. In the picture, it can be found that the simulated responses of output voltage with the lag controller have a voltage ripple of 2.4 v and a settling time of 0.02 s, while the output voltage with designed FSFSM controller has a voltage ripple of 2.1 v and a settling time of 0.003 s under the same condition. Figures 23(a) and 23(b) show the experimental responses of output voltage under load variation. From the both figures, it can be found that the experimental results of output voltage with lag controller have a voltage ripple of 2.6 v and settling time of 0.2 s, whereas the output voltage using the designed FSFSM controller has a voltage ripple of 2.0 v and settling time of 0.15 s.

203793.fig.0022
Figure 22: Simulated responses of output voltage for lag controller and FSFSM controller for load voltage step change from 20 mΩ to 16 mΩ (−20% load variations).
fig23
Figure 23: Experimental responses of output voltage for (a) lag controller and (b) FSFSM controller for load step change from 20 mΩ to 16 mΩ (−20% load variations).
4.2. Simulation and Experiment Results of FSFSM Controller and DISM Controller
4.2.1. Startup Transient

Figure 24 shows the simulated start-up responses of output voltage using the FSFSM controller and DISM controller. It can be seen that the risetime of DISM controller is smaller than that of FSFSM controller. Meanwhile, the setting time of FSFSM controller and DISM controller are 0.014 s and 0.01 s, respectively. Also, it is clearly found that the steady-state error of DISM controller is much smaller than that of FSFSM controller.

203793.fig.0024
Figure 24: Simulated start-up responses of output voltage for FSFSM controller and DISM controller.
4.2.2. Line Variation

Figure 25 shows the simulated responses of output voltage under line variation for input voltage step change from 144 v to 172.8 v (+20% line variations) at 0.05 s. In the picture, it can be found that the simulated responses of output voltage with both controllers have negligible change under this condition. They showed a good robustness against line variation.

203793.fig.0025
Figure 25: Simulated responses of output voltage for FSFSM controller and DISM controller for input voltage step change from 144 v to 172.8 v (+20% line variations).

Figure 26 shows the simulated responses of output voltage with FSFSM controller and DISM controller under line variation for line step change from 144 v to 115.2 v (−20% line variations) at 0.05 s. It is clearly found that the simulated responses of output voltage with FSFSM controller and DISM controller have a setting time of 0.014 s and 0.01 s, respectively, and negligible change under this condition as well. However, both results have serious oscillation to compare with the response which is shown in Figure 25 at the beginning.

203793.fig.0026
Figure 26: Simulated responses of output voltage for FSFSM controller and DISM controller for input voltage step change from 144 v to 115.2 v (−20% line variations).
4.2.3. Load Variation

Figure 27 depicts the simulated responses of output voltage of the two-stage converter, which are performed with FSFSM controller and DISM controller, respectively, for load step change from 20 mΩ to 24 mΩ (+20% load variations) at 0.05 s. In Figure 27, it can be found that the simulated results of output voltage using the FSFSM controller have a voltage ripple of 2.2 v and a settling time of 0.003 s, whereas the output voltage with the designed DISM controller has a voltage ripple of 2.21 v and a settling time of 0.0025 s. Obviously, the FSFSM controller has a lower voltage ripple. However, it is clearly found that DISM controller has a quicker settling time and a much smaller steady-state error.

203793.fig.0027
Figure 27: Simulated responses of output voltage for FSFSM controller and DISM controller for input voltage step change from 20 mΩ to 24 mΩ (+20% load variations).

Figure 28 depicts the simulated results of output voltage under load variation for load step change from 20 mΩ to 16 mΩ (−20% load variations) at 0.05 s.

203793.fig.0028
Figure 28: Simulated responses of output voltage for FSFSM controller and DISM controller for load voltage step change from 20 mΩ to 16 mΩ (−20% load variations).

In the picture, it can be found that the simulated responses of output voltage with the FSFSM controller have a voltage ripple of 2.1 v and a settling time of 0.003 s, while the output voltage with designed DISM controller has a voltage ripple of 2.11 v and a settling time of 0.0025 s under the same condition. Comparing both responses, it is clearly found that the FSFSM controller has a lower voltage ripple and DISM controller has a quicker settling time and a much smaller steady-state error. However, both results have serious oscillation to compare with the responses which are shown in Figure 27 at the beginning.

From Figure 24 to Figure 28, it is clearly identified that both FSFSM controller and DISM controller are capable of offering good dynamical response to the two-stage converter and good large-signal operations with fast dynamical responses. However, it is noted that DISM controller has a quicker settling time and a negligible steady-state error, which means that DISM controller can eliminate steady-state error.

5. Conclusions

This paper proposed a fixed switching frequency sliding mode controller and double-integral sliding mode controller for the two-stage dc-dc converter over a wide range of conditions. The theoretical analysis, design, and output voltage regulation operated in CCM have been successfully demonstrated. In order to prove the good performance of the proposed FSFSM controller, a lag controller is chosen as the comparison and several simulations and experiment results are presented. In consequence, all the results show that FSFSM controller is capable of offering good dynamical response and good large-signal operations with fast dynamical response to the converter in comparison with lag controller. A major merit over the lag controller lies in the fact that the FSFSM controller and DISM controller are robust to large variations on line, load variations, and startup response without modifying the sliding coefficients. As a further study, we also give some simulation results of FSFSM controller and DISM controller to briefly prove that DISM controller can eliminate the steady-state error. In a word, the FSFSM controller is feasible and appropriate to the two-stage converter to implement good steady and dynamical responses and the DISM controller is a promising method for the converter to eliminate the steady-state error.

Conflict of Interests

The authors declare that there is no conflict of interests regarding the publication of this paper.

Acknowledgments

This work is supported by the Natural Science Foundation project of CQ CSTC2013yykfC60005, CSTC2013jcsf-jcssX0022, and NSFC (Grant No.11247325).

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