Formation and Device Application of Ge Nanowire Heterostructures via Rapid Thermal Annealing
Figure 10
Electrical characteristics of Ge nanowire back-gate FETs (with Al2O3 capping during annealing) at 300 K. (a) Schematic illustration of a Ge nanowire back-gate FET. (b) curves of the back-gate Ge nanowire transistor after RTA, showing a p-type MOSFET behavior. (c) curves of the back-gate Ge nanowire transistor after RTA. (d) Dual sweepings of the gate bias between +40 V to −40 V showing different sizes of hysteresis under various conditions. The arrows indicate the sweeping directions. The hysteresis was significantly reduced after Al2O3 passivation. A small hysteresis was still observed after ALD, which may be attributed to the charge trapping on the Ge surface between the Ge nanowire channel and the back-gate dielectric, the region that is not covered by the Al2O3 capping layer. Reproduced from [14].
