Formation and Device Application of Ge Nanowire Heterostructures via Rapid Thermal Annealing
Figure 9
Electrical characterization of Ge nanowire back-gate FETs (without Al2O3 capping during annealing) at 300 K. (a) Schematic illustration of a Ge nanowire back-gate FET. (b) curves of the back-gate Ge nanowire transistor before and after RTA, both showing a p-type MOSFET behavior. The transistor performance was significantly improved after RTA, in which the Ni2Ge source/drain contacts were formed. Reproduced from [13].
