A Substrate-and-Gate Triggering NMOS Device for High ESD Reliability in Deep Submicrometer Technology
Figure 5
(a) versus resistance characteristics among the GGNMOS and resistance SGTNMOS. (b) versus characteristics among the GGNMOS and RC-SGTNMOS. (c) versus resistance characteristics among the GGNMOS and resistance SGTNMOS. (d) versus resistance characteristics among the GGNMOS and RC SGTNMOS.