A Novel Soft-Switching Synchronous Buck Converter for Portable Applications

Abstract

This paper proposes a zero-voltage-transition (ZVT) pulse-width-modulated (PWM) synchronous buck converter, which is designed to operate at low voltage and high efficiency typically required for portable systems. A new passive auxiliary circuit that allows the main switch to operate with zero-voltage switching has been incorporated in the conventional PWM synchronous buck converter. The operation principles and a detailed steady-state analysis of the ZVT-PWM synchronous converter implemented with the auxiliary circuit are presented. Besides, the main switch and all of the semiconductor devices operate under soft-switching conditions. Thus, the auxiliary circuit provides a larger overall efficiency. The feasibility of the auxiliary circuit is confirmed by simulation and experimental results.

1. Introduction

Current trends in consumer electronics demand progressively lower-voltage supplies. Portable electronics equipment, such as laptop computers, cellular phones, and future microprocessor and memory chips, requires low-power circuitry to maximize battery run time. Because of significantly lower conduction losses, synchronous rectifiers are now used in essentially all low-voltage DC power supplies [1–4]. A synchronous rectifier is an electronic switch that improves power-conversion efficiency by placing a low-resistance conduction path across the diode rectifier in a switch-mode regulator. MOSFETs usually serve this purpose.

However, higher input voltages and lower output voltages have brought about very low duty cycles, increasing switching losses and decreasing conversion efficiency. So in this paper, we have optimized the efficiency of the synchronous buck converter by eliminating switching losses using soft-switching technique. The voltage-mode soft-switching method that has attracted most interest in recent years is the zero-voltage transition [5–24]. This is because of its low additional conduction losses and because its operation is closest to the PWM converters. The auxiliary circuit of the ZVT converters is activated just before the main switch is turned on and ceases after it is accomplished. The auxiliary circuit components in this circuit have lower ratings than those in the main power circuit because the auxiliary circuit is active for only a fraction of the switching cycle; this allows a device that can turn on with fewer switching losses than the main switch to be used as the auxiliary switch. The improvement in efficiency caused by the auxiliary circuit is mainly due to the difference in switching losses between the auxiliary switch and the main power switch if it were to operate without the help of the auxiliary circuit. Previously proposed ZVT-PWM converters have at least one of the following key drawbacks. (i) The auxiliary switch is turned off while it is conducting current. This causes the switching losses and EMI to appear, which offsets the benefits of using the auxiliary circuit. In converters such as the ones proposed in [6, 12, 15, 16], the turnoff is very hard. (ii) The auxiliary circuit causes the main converter switch to operate with a higher peak current stress and with more circulating current. This results in the need for a higher current-rated device for the main switch and an increase in conduction losses. The converters proposed in [5, 8, 9, 13, 14, 17] are having high current stresses on the main switch. (iii) The auxiliary circuit components have high voltage and/or current stresses, such as converters proposed in [5, 8, 9, 14, 17]. The converter proposed in [23] reduces the current stress on the main switch, but the circuit is very complex. (iv) In addition, most active circuits are seriously criticized due to their complexity, high cost, difficult control, large circulating energy, excessive voltage and current stresses, and also narrow line and load ranges. Additionally, it has been reported that the passive circuits are cheaper and more reliable and have a higher performance/cost ratio than the active ones [25, 26].

Reducing switching losses for low-power circuit such as synchronous buck is not known to be present in the literatures [1–26]. The converter shown in Figure 1 is designed for a low-voltage, high-current circuit, and it is found to be highly efficient. Hence, this paper presents a new class of ZVT synchronous buck converters. By using a resonant auxiliary network, the proposed converters achieve zero-voltage switching for the main switch and synchronous switch, and zero-current switching for the auxiliary switch without increasing their voltage and current stresses.

Figure 1 

The proposed synchronous buck converter.

The paper is organized as follows. Section 2 gives a short description of the proposed circuit followed by a review of the various modes of operation with their key waveforms and the representation of their equivalent operation modes and analysis. Section 3 presents the design considerations and Section 4 includes basic features of the converter. Section 5 includes simulation and experimental results to illustrate the features of the proposed converter scheme. Section 6 includes some conclusions.

2. The ZVT-PWM Synchronous Buck Converter

2.1. Circuit Description and Assumption

The ZVT-PWM synchronous buck converter is shown in Figure 1. It is the combination of the conventional PWM synchronous buck converter and the proposed auxiliary snubber circuit. The auxiliary circuit consists of a resonant inductor 𝐿_r, resonant capacitor 𝐶_r, a buffer capacitor 𝐶_b, and three auxiliary Schottky diodes 𝐷_S1, 𝐷_S2, and 𝐷_S3. Body diodes of main switch S and synchronous switch S₁ are also utilized in this converter.

To analyze the steady-state operations of the proposed circuit, the following assumptions are made during one switching cycle.

(1)Input voltage 𝑉_i is constant.(2)Output voltage 𝑉_o is constant or output capacitor 𝐶_o is large enough.(3)Output current 𝐼_o is constant or output inductor 𝐿_o is large enough.(4)Output inductor 𝐿_o is much larger than resonant circuit inductor 𝐿_r.(5)Resonant circuits are ideal.(6)Semiconductor devices are ideal.(7)Reverse recovery time of all diodes is ignored.

2.2. Operation Principles and Analysis

Based on these assumptions, circuit operations in one switching cycle can be divided into eight stages. The key waveforms of these stages are given in Figure 2 and the equivalent circuit schemes of the operation stages are given in Figure 3. The detailed analysis of every stage is presented as follows.

Figure 2 

Key theoretical waveforms of the proposed converter.

(a)

(b)

(c)

(d)

(e)

(f)

(g)

(h)

Figure 3 

Modes of operation.

Mode 1 t₀-t₁. Prior to t₁, the body diode of switch S₁ was conducting, while the main switch S was off. The equations 𝑖_S=0, 𝑖_𝐷1=𝐼_o, 𝑖_𝐿r=0, 𝑣_𝐶r=0, 𝑣_𝐶b=0 are valid at the beginning of this stage. At t = t₀, the main switch is turned on, which realizes zero-current turn-on as it is in series with the resonant inductor 𝐿_r. During this stage, 𝑖_𝐿r rises and current i_D1 through body diode of switch S₁ falls simultaneously at the same rate linearly. The mode ends at t = t₁ when 𝑖_𝐿r reaches 𝐼_o and i_D1 becomes zero. The body diode D₁ is turned off with ZVS because of 𝐶_r and 𝐶_b being existent. In this state, 𝑖_S=𝑖_𝐿r=𝑉ⁱ𝑖_𝐷1𝐿_r𝑡−𝑡⁰,=𝐼_o−𝑖_𝐿r=−𝑉ⁱ𝐿_r𝑡−𝑡⁰+𝐼^o𝑡₀₁,=𝐿^r𝑉_i𝐼_o.(1)

Mode 2 t₁-t₂. The diode 𝐷_S2 starts conducting at the instant when body diode D₁ is turned off. At t = t₁, 𝐼_S=𝑖_𝐿r=𝐼_o, i_D1 = 0, 𝑣_𝐶r=0, and 𝑣_𝐶b=0. In this interval, resonance occurs with the inductor 𝐿_r and capacitors 𝐶_r and 𝐶_b. This mode ends with 𝐶_r charged up to the input voltage 𝑉_i; 𝑖_𝐿r𝑡−𝑡¹=𝑉ⁱ𝑍₁𝑣_𝐶rsin𝜔₁𝑡−𝑡¹+𝐼^o,𝑣_𝐶b𝑡−𝑡¹=𝐶𝐶^𝑒_r−𝑉ⁱcos𝜔₁𝑡−𝑡¹+𝑉ⁱ,𝑡−𝑡¹=𝐶𝐶^𝑒_b−𝑉ⁱcos𝜔₁𝑡−𝑡¹+𝑉ⁱ,(2) where 𝐶_𝑒=𝐶^r𝐶_b𝐶_r+𝐶_b𝜔₁,=1√𝐿_r𝐶_𝑒𝑍₁,=𝐿_r𝐶_𝑒.(3) The diode 𝐷_S1 is turned on with ZVS at the moment when 𝑣_𝐶r becomes 𝑉_i. In this state, 𝑡₁₂=1𝜔₁sin⁻¹𝐶^r𝐶_𝑒−1.(4)

Mode 3 t₂-t₃. At t = t₂, 𝑖_S=𝐼_o, 𝑖_𝐿r=𝑖_𝐿rmax, 𝑣_𝐶r=𝑉_𝐶rmax=𝑉_i, and 𝑣_𝐶b=𝑉_𝐶b1. When diode 𝐷_S1 turns on, new resonance starts with 𝐿_r and 𝐶_b. This mode ends when 𝑖_𝐿r becomes equal to load current 𝐼_o, and 𝐶_b is charged up to its maximum voltage 𝑉_𝐶b𝑚. Both diodes 𝐷_S1 and 𝐷_S2 are turned off under ZCS due to the existence of 𝐿_r. The voltage and current expressions that govern this circuit mode are given by 𝑖_𝐿r𝑡−𝑡²=−𝐼𝑉^𝐿rmax_𝐶b1−𝐼_ocos𝜔²𝑡−𝑡²𝑍₂𝑣_𝐶bsin𝜔₂𝑡−𝑡²+𝐼^o,𝑡−𝑡²=+𝐼𝑉^𝐿rmax_𝐶b1−𝐼_o𝑍²sin𝜔₂𝑡−𝑡²cos𝜔₂𝑡−𝑡².(5) The time interval of this stage can be found as follows: 𝑡₂₃=1𝜔₂tan⁻¹𝐼^𝐿rmax−𝐼_o𝑉_𝐶b1,(6) where 𝜔₂=1√𝐿_r𝐶_b𝑍₂,=𝐿_r𝐶_b.(7)

Mode 4 t₃-t₄. Since both diodes 𝐷_S1 and 𝐷_S2 have been turned off at t₃, now only the main switch S and inductor 𝐿_r carry the load current. There is no resonance in this mode and the circuit operation is identical to that of a conventional PWM buck converter. The voltage and current equations for this mode are 𝑖_S=𝑖_𝐿r=𝐼_o.(8)

Mode 5 t₄-t₅. This mode starts with the initial conditions 𝑖_S=𝐼_o, 𝑖_𝐿r=𝐼_o, 𝑣_𝐶r=𝑉_𝐶rmax=𝑉_i, 𝑉_𝐶b=𝑉_𝐶b𝑚. The main switch is turned off under ZVS, and at the same instant, the synchronous switch is turned on under ZCS. Since the synchronous switch S₁ is conducting the voltage across capacitor, 𝐶_b is clamped to zero. Resonance occurs with 𝐿_r and 𝐶_r. The voltage and current equations for this mode are 𝑖𝑣_𝐶b𝑡−𝑡⁴=0,_𝐿r𝑣𝑡−𝑡⁴=𝐼^ocos𝜔₃𝑡−𝑡⁴−𝑍𝑉ⁱ₃sin𝜔₃𝑡−𝑡⁴,(9)_𝐶r𝑡−𝑡⁴=𝐼^o𝑍₃sin𝜔₃𝑡−𝑡⁴+𝑉ⁱcos𝜔₃𝑡−𝑡⁴.(10)

The time duration of this mode can be found as follows: 𝑡₄₅=1𝜔₃tan⁻¹𝑉_i𝐼_o𝑍₃,(11) where 𝜔₃=1√𝐿_r𝐶_r𝑍₃,=𝐿_r𝐶_r.(12) This mode ends when voltage across 𝐶_r becomes zero. Therefore, the diode 𝐷_S2 turns on under ZVS.

Mode 6 t₅-t₆. In this stage, new resonance takes place through 𝐿_r-𝐶_b-𝐷_S2-𝐷_S1. At t = t₅, 𝑖_S = 0, 𝑖_𝐿r=𝐼_𝐿r2, 𝑣_𝐶r=0, and 𝑣_𝐶b=0 are initial conditions for this mode. For this state, the equations are 𝑣𝑖^𝐶b_𝐿r𝑡−𝑡⁵=𝐼^𝐿r2𝑍₂sin𝜔₂𝑡−𝑡⁵,𝑡−𝑡⁵=𝐼^𝐿r2cos𝜔₂𝑡−𝑡⁵.(13) When 𝑖_𝐿r becomes 𝐼_o, this mode comes to an end. The time interval for this mode is given as 𝑡₅₆=1𝜔₂tan⁻¹𝐼^o𝐼_𝐿r2,(14) where 𝜔₂=1√𝐿_r𝐶_b𝑍₂,=𝐿_r𝐶_b.(15)

Mode 7 t₆-t₇. At t = t₆, 𝑖_S=0, 𝑖_𝐿r=𝐼_o, 𝑣_𝐶r=0, and 𝑣_𝐶b=𝑉_𝐶b2 are initial conditions for this mode. As 𝑖_𝐿r becomes 𝐼_o, synchronous switch is turned off under ZCS. Stored energy of inductor 𝐿_r and capacitor 𝐶_b is now transferred to load. ON state resistances of diodes and switches are neglected. The voltage and current equations for this mode are given as 𝑣_𝐶b𝑡−𝑡⁶=−𝐼^o𝐶_b𝑡−𝑡⁶+𝑉^𝐶b2𝑖_𝐿r,𝑡−𝑡⁶=−𝐿𝑉^o_r𝑡−𝑡⁶+𝐼^o.(16) This mode ends when 𝑖_𝐿r becomes zero. The interval of this mode is given by 𝑡₆₇=𝐼^o𝐿_r𝑉_o.(17)

Mode 8 t₇-t₈. Now the load current will flow through body diode of synchronous switch S₁. During this mode, the converter operates like a conventional PWM buck converter until the switch S is turned on in the next switching cycle. In this mode, 𝑖_𝐷1=𝐼_o.(18)

2.3. Output Voltage

The output voltage can be specified by evaluating the energy from the supply, through the input resonant inductor 𝐿_r [27]. The output voltage is given by 𝑉_o=𝑉ⁱ𝜏12𝑡⁰¹=𝑉_i+𝑡₁₂+𝑡₂₃+𝑡₄₅+𝑡₅₆+𝑡₆₇𝜏⎛⎜⎜⎜⎝12𝐼^o𝐿_r𝑉_i+1𝜔₁sin⁻¹𝐶^r𝐶_𝑒−1+1𝜔₂tan⁻¹𝐼^𝐿rmax−𝐼_o+1𝑉_𝐶b1𝜔₃tan⁻¹𝑉^𝐶rmax𝐼_o𝑍₃+𝜔1₂tan⁻¹𝐼^o𝐼_𝐿r2+12𝐼^o𝐿_r𝑉_o⎞⎟⎟⎟⎠.(19)

Since time intervals of Modes 1 and 7 have low value as compared to other terms in the above expression, the first and last terms are neglected for simplification.

Then, the voltage conversion ratio will be 𝑉_o𝑉_i=1𝜏⎛⎜⎜⎜⎝1𝜔₁sin⁻¹𝐶^r𝐶_𝑒−1+1𝜔₂tan⁻¹𝐼^𝐿rmax−𝐼_o+1𝑉_𝐶b1𝜔₃tan⁻¹𝑉^𝐶rmax𝐼_o𝑍₃+𝜔1₂tan⁻¹𝐼^o𝐼_𝐿r2⎞⎟⎟⎟⎠,(20) where 𝜏=1/𝑓_S,and𝑓_S is the switching frequency.

From the expression, it can be seen that the voltage conversion ratio depends upon switching frequency rather than duty ratio.

3. Design Procedure

Design of conventional PWM converters has been well presented in literatures. Thus, it is more significant to focus on design procedures of the auxiliary circuit. The resonant inductor and resonant capacitor are the most important components when designing the auxiliary circuit. The proposed auxiliary resonant circuit provides soft-switching conditions for the main transistor. The following design procedure is developed considering procedures such as those presented previously in [5–7].

(1)Snubber inductor 𝐿_r is selected to permit its current to rise up to at most the maximum output current within 𝑡_r time periods, during the turn-on of the main transistor or the turnoff of the synchronous switch. In this case, from (1), 𝑉_i𝐿_r𝑡_r≤𝐼_omax(21) can be written. Here, 𝑡_r is the rise time of the main transistor. These equations provide ZCS turn-on for the main transistor and ZVS turnoff for the body diode of synchronous switch.(2)Snubber capacitor 𝐶_r is selected to be discharged from 𝑉_i to zero with the maximum output current over at least the time period t_f during the turnoff of the main transistor. For this state, according to (10) and (11), 1𝐼_omax𝑍₃𝑉_i≥𝑡_𝑓.(22) Here, t_f is the fall time of the main transistor and 𝑍₃=𝐿_r𝐶_r.(23)(3)Buffer capacitor 𝐶_b is selected to be charged from zero up to at most a value decided before, such as half the input voltage. This capacitor takes on the energies that are stored in the snubber inductor during the turnoff of the synchronous switch and charge of the snubber capacitor. This energy balance can be defined as follows: 12𝐶^r𝑉²_i+12𝐶^b𝑉^2𝐶_b𝑚=12𝐿^r𝐼^2omax.(24) The value of 𝐶_b is normally larger than the value of 𝐶_r. Consequently, the bigger the value of selected 𝐶_b is, the lower the value of 𝑉_𝐶bmax will be. Moreover, if the value of 𝐶_b increases, the voltage across the synchronous switch falls, but the time periods t₂₃, t₄₅, t₅₆, and t₆₇ during which the inductor energies are transferred to 𝐶_b or the load rise.

4. Converter Features

The features of the proposed soft-switching converter are briefly summarized as follows.

(1)All of the active and passive semiconductor devices are turned on and off under exact ZVS and/or ZCS.(2)The proposed converter has a simple structure, low cost, and ease of control.(3)The converter acts as a conventional PWM converter during most of the switching cycles.(4)The presented snubber cell can be easily applied to the other basic PWM DC-DC converters and to all switching converters.(5)The proposed converter has a larger total efficiency and a wider load range.(6)The main switch and the auxiliary switch are not subjected to additional voltage stresses. Current stress on the main switch is slightly higher, but current stress on the auxiliary switch is within safe limit.

5. Simulation and Experimental Results

A prototype of the proposed converter, as shown in Figure 1, has been built in the laboratory. The newly proposed converter operates with an input voltage 𝑉_i=12V, output voltage 𝑉_o=3.3V, load current of 11 A, and a switching frequency of 500 kHz. The converter is simulated using simulation software PSIM, version 6.0. The major parameters and components are given in Table 1.

Table 1 

Components used in the proposed converter.

Figures 4(a)–4(d) show the simulation results of the proposed converter and Figures 5(a)–5(d) present the experimental results. All the waveforms except the efficiency curve represent a time period of one switching cycle, which is 2 microseconds in this case. The amplitudes are denoted in Figure 4 with each of their waveforms, respectively.

(a)

(b)

(c)

(d)

Figure 4 

Simulated voltage and current waveforms: (a) main switch $\text{S}$: $V_{\text{S}}$, $I_{\text{S}}$; (b) synchronous switch ${\text{S}}_1$: $V_{\text{S}1}$, $I_{\text{S}1}$; (c) diode $D_{\text{S}1}$ and capacitor $C_{\text{r}}$; (d) capacitor $C_{\text{b}}$ and diode $D_{\text{S}3}$.

(a)

(b)

(c)

(d)

Figure 5 

Experimental voltage and current waveforms: (a) main switch $\text{S}$: $V_{\text{S}}$, $I_{\text{S}}$ (V: 5 V/div, I: 10 A/div, time: 0.2 μs/div); (b) synchronous switch ${\text{S}}_1$: $V_{\text{S}1}$, $I_{\text{S}1}$ (V: 5 V/div, I: 10 A/div, time: 0. 2 μs/div); (c) diode $D_{\text{S}1}$ and capacitor $C_{\text{r}}$: $V_{D\text{S}1}$, $V_{C\text{r}}$ (V: 5 V/div, I: 2 V/div, time: 0. 2 μs/div); (d) capacitor $C_{\text{b}}$ and diode $D_{\text{S}3}$: $V_{C\text{b}}$, $V_{D\text{S3}}$ (V: 5 V/div, I: 2 V/div, time: 0.2 μs/div).

5.1. Main Switch S

It is noted from Figures 4(a) and 5(a) that the main switch S is turned on under ZCS, and the body diode D₁ of synchronous switch S₁ is turned off under ZVS. The main switch takes the load current and the charging current of the capacitors 𝐶_r and 𝐶_b. The inductor starts to transfer its stored energy to capacitors 𝐶_r and 𝐶_b during the turn-on period of main switch. The converter has not exceeded the voltage limits; however, the current stress is slightly higher for a very short period of time. The main switch also switches off under ZVS. The current and voltage wave shapes are identical to theoretical waveforms.

5.2. Synchronous Switch S₁

After the main switch is turned on under ZCS, the body diode of synchronous switch is turned off under ZVS, which can be observed from Figures 4(b) and 5(b). The synchronous switch is turned on under ZCS when the main switch is turned off under ZVS. After the turnoff of the main switch, both capacitors 𝐶_r and 𝐶_b are discharged. As soon as both capacitors are discharged near zero, the body diode of synchronous switch S₁ is turned on under ZVS. The converter has not exceeded the current limits; however, the voltage stress across the switch is slightly higher for a very short period of time. The synchronous switch operates within the safe limits, and it can be noted here that the conduction period of S₁ is more confining to the design values and it operates at a low power when compared to the other switches. The shapes of the figures are identified to confine much to the theoretical waveforms.

5.3. Schottky Diodes 𝐷_S1, 𝐷_S2, and 𝐷_S3

The Schottky diodes work for a very short period to discharge the resonant capacitors 𝐶_r and 𝐶_b as can be observed from Figures 4(c), 4(d), 5(c), and 5(d). Moreover, it can be seen that the Schottky diodes 𝐷_S1, 𝐷_S2, and 𝐷_S3 operate under soft-switching conditions. The Schottky diodes are turned on and off under ZVS. The conduction of Schottky diodes may cause a considerable drop in output voltage for low-power circuits, but due to the advancement in semiconductor techniques, Schottky diodes are also now available with a low-forward-voltage drop for high-frequency circuits.

Additionally, during the turn-on and turnoff of main switch S and synchronous switch S₁, a slight overlap occurs between their own voltages and currents. Therefore, the switching losses are zero, but a little additional conduction loss takes place, and so the conduction losses dominate the total loss in the soft-switching converter.

Efficiency Curve
From Figure 6, it can be observed that the efficiency values of the soft-switching converter are relatively high with respect to those of the hard-switching converter. The efficiency values towards the minimum output power decrease naturally because the converter is designed for the maximum output current. At 70% output power, the overall efficiency of the proposed converter increases to about 96% from the value of 87% in its counterpart hard-switching converter. The high efficiency concludes the correctness of the design values.

Figure 6 

Efficiency curve.

6. Conclusion

The concepts of ZVT used in medium and high power were implemented in synchronous buck converter, and it was shown that the switching losses in synchronous buck were eliminated. Besides, the main switch ZCS is turned on and ZVS is turned off. The synchronous switch is also turned on under ZCS and turned off under ZVS. Hence, switching losses are reduced and the newly proposed ZVT synchronous buck is highly efficient than the conventional converter. The additional voltage and current stresses on the main devices do not take place, and the auxiliary devices are subjected to allowable voltage and current values. Moreover, the converter has a simple structure, low cost, and ease of control. A prototype of a 3.3 V, 11 A, 500 kHz system was implemented to experimentally verify the improved performance.