One Clock-Cycle Response 0.5 𝜇m CMOS Dual-Mode ΣΔ DC-DC Bypass Boost Converter Stable over Wide 𝑅_ESRLC Variations

Abstract

Power supplies in portable applications must not only conform and adapt to their highly integrated on-chip and in-package environments but also, more intrinsically, respond quickly to fast load dumps to achieve and maintain high accuracy. The frequency-compensation network, however, limits speed and regulation performance because it must cater to all combinations of filter capacitor 𝐶_𝑂, inductor L, and 𝐶_𝑂's equivalent series resistance 𝑅_ESR resulting from tolerance and modal design targets. As such, it must compensate the worst-case condition and therefore restrain the performance of all other possible scenarios, even if the likelihood of occurrence of the latter is considerably high and the former substantially low. Sigma-delta (ΣΔ) control, which addresses this issue in buck converters by easing its compensation requirements and offering one-cycle transient response, has not been able to simultaneously achieve high bandwidth, high accuracy, and wide 𝑅_ESRLC compliance in boost converters. This paper presents a dual-mode ΣΔ boost bypass converter, which by using a high-bandwidth bypass path only during transient load-dump events was experimentally 1.41 to 6 times faster than the state of the art in current-mode ΣΔ boost supplies, and this without any compromise in 𝑅_ESRLC compliance range (0–50 mΩ, 1–30 𝜇H, and 1–350 𝜇F).

1. Introduction

In portable applications like cellular phones, PDAs, and the like, integrated BiCMOS and CMOS switching dc-dc supply circuits reduce cost, size, component count, and design complexity (from a user’s perspective). One of the critical bottlenecks in obtaining a fully integrated solution, however, is the frequency-compensation circuit, which is designed around off-chip power LC filter devices to obtain optimal performance [1]. The fact is mode-rich state-of-the-art applications, manufacturing tolerances, and parameter drifts expose dc-dc converter integrated circuits (ICs) to wide variations in output capacitance C_O, power inductance L, and C_O’s equivalent series resistance 𝑅_ESR, inducing considerable changes in loop-gain and transient response, compromising feedback stability or transient response. As a result, to guarantee stability and high bandwidth with a fixed on-chip frequency-compensation circuit, the design necessarily constrains 𝑅_ESRLC values within a narrow target range [1]. This is especially detrimental in compact high-performance multiple input-output converters [2, 3], where the on-chip or in-package LC filter is variable by design to dynamically accommodate the diverse loading conditions of the system.

Unclocked or asynchronous sigma-delta (ΣΔ) buck converters [4–8] are self-compensating and free of the speed-stability tradeoffs of most dc-dc converters because the control loop in these converters resembles current-mode control by indirectly sensing the inductor current ripple via the ripple voltage it drops across C_O’s 𝑅_ESR. In other words, the ESR voltage mostly sets the terminal ripple voltage of C_O, impressing the inductor ripple current information on the output voltage and achieving current-mode-like control. The resulting single-pole-like response yields higher bandwidth and more explicit control over the output ripple voltage [7].

Extending this technique and its benefits to boost converters, which are popular in portable electronics for boosting battery voltages to 3.3–5 V, is not straightforward because the inductor current does not fully flow to C_O. Consequently, in realizing ΣΔ control in boost converters, the feedback circuit must explicitly sense and mix inductor current with the sensed output voltage [9]. Such techniques, however, resurrect the limiting speed-stability tradeoffs ΣΔ control averted in buck converters in the first place, forcing the designer to adjust current and voltage gains thereby reducing the loop bandwidth in order to accommodate large𝑅_ESRLC filter values.

This paper presents a dual-mode boost ΣΔ bypass controller IC that overcomes the aforementioned speed-stability compromise by introducing a high-speed bypass mode (and circuit) that engages only during transient load-dump events, achieving both high bandwidth and wide 𝑅_ESRLC compliance. To this end, Section 2 first reviews and discusses the stability requirements of ΣΔ converters and their resulting transient response to fast load dumps. Section 3 then describes the proposed dual-mode technique and the design of its IC-prototype embodiment, followed by experimental results in Section 4; Section 5 draws relevant conclusions.

2. ΣΔ Converters

2.1. ΣΔ Control in Buck Converters

AΣΔbuck converter, as shown in Figure 1, controls the frequency and duty cycle of PMOS switch S_M by comparing rippling output voltage v_O via sensed voltage 𝑣_S against dc reference 𝑉_REF with comparator CP_V. Operationally, ac inductor ripple current i_l flows into C_O and its 𝑅_ERS (which is relatively large in these converters at 100–250 mΩ to ensure its voltage —𝑣_esr— overwhelms ac capacitor voltage v_c) [7] as capacitor displacement current i_c, forcing ac output ripple voltage v_o to mimic i_l (v_o≈𝑣_esr=i_l𝑅_ESR). As a result, in regulating v_o, the converter also regulates i_l, which in the process simplifies the frequency response of the converter to that of a single-pole system, as in current-mode control, guaranteeing stability, irrespective of 𝑅_ESRLC values.

Figure 1 

Circuit schematic of a switching ΣΔbuck converter.

In a positive load-step transient event, when load current i_O suddenly rises, comparator CP_V detects the voltage droop the now larger i_O induces on v_O and consequently switches S_M on indefinitely (i.e., at 100% duty cycle) until v_O returns within CP_V’s predefined hysteretic window limits, that is, within an acceptably low margin of 𝑉_REF. During S_M’s on time, the inductor voltage being nearly constant at V_IN − V_O, inductor current i_L slews in a single switching cycle until it fully supplies i_O and recharges C_O back to 𝑉_REF [8]. In other words, only the inductor and capacitor slew-rate limits and second-order delays across the comparator and switch set the response time (effective bandwidth) of the system. Note a negative load dump undergoes a similar but reversed response.

2.2. ΣΔ Control in Boost Converters

Unlike buck converters, ac inductor ripple current i_l in boost converters does not flow completely to output capacitor C_O because reverse-biased diode D (shown in Figure 2) temporarily disconnects L from v_O (and C_O) when switch S_M conducts all of i_L to ground. The resulting ac ripple voltage in v_O does not fully reflect the behavior of i_l, as it does in buck converters with nonnegligible 𝑅_ESRvalues, which means that ΣΔ control in boost converters cannot rely on v_O alone [9]. The negative feedback loop in a boosting supply must therefore sense, scale, and mix i_L with v_O explicitly (e.g., mix i_LR_Ig_mi and v_Og_mv into R_S as scaled sum 𝑣_SUM) to achieve current-mode-like control characteristics. A hysteretic comparator then modulates S_M’s frequency and duty cycle based on how the scaled sum (𝑣_SUM) of the ripples compares against a user-defined hysteresis window. Note the voltage feedback loop modulates the effective inductor reference current 𝑣_𝐼.REF/R_I, which is also the average inductor current I_L (or low-pass filtered —LPF— version of i_L) to whatever is necessary to fully supply i_O.

Figure 2 

Circuit schematic of a switching ΣΔ boost converter.

Within the context of averaged small-signal analysis, the relatively high-gain, low-bandwidth voltage control loop (V Loop) of the system effectively embeds a higher bandwidth, lower gain current loop (I Loop), as shown Figure 3 [10]. At low frequencies, below low-pass filter pole 𝑝_LPF, i_LR_I nearly equals 𝑣_𝐼.REF and the gain of the current loop is practically zero, but increasing with frequency until reaching its highest possible gain at frequencies past 𝑝_LPF. The current loop’s gain again drops at high frequencies, past the complex LC double poles, when the ac voltage across L decreases. Given that i_L is, for all practical purposes, regulated to higher frequencies and therefore is a current source to the outer voltage loop at moderate-to-high frequencies, C_O and effective load resistance R_O set the dominant low-frequency pole of the system while L and R_O invoke right-half plane zero 𝑧_RHP [11].

Figure 3 

Small-signal equivalent control diagram of switching ΣΔ boost converter at moderate-to-high frequencies.

For stable conditions to prevail, the unity-gain frequency of the voltage loop (i.e., the system —𝑓_𝑉.0dB—) must fall below 𝑧_RHP and i_L must remain a current source (i.e., current loop must stay closed with considerable loop gain) for the frequency range of interest to the voltage loop [10]. As such, 𝑓_𝑉.0dB must stay below both 𝑧_RHP and current-loop bandwidth 𝑓_𝐼.0dB:𝑓_0dBV≈𝑔_𝑚𝑣𝐷^′_𝑀2𝜋𝑅_𝐼𝑔_𝑚𝑖𝐶_𝑂<<𝑓_0dBI≈𝑅_𝐼𝑔_𝑚𝑖𝑅_𝑆𝑀𝑉_𝑂,2𝜋𝐿 (1)𝑓_0dBV≈𝑔_𝑚𝑣𝐷^′_𝑀2𝜋𝑅_𝐼𝑔_𝑚𝑖𝐶_𝑂<𝑧_RHP=𝐷^′_𝑀𝑉_𝑂2𝜋𝐿𝐼_𝐿, (2) or 𝐿𝐼_𝐿𝑉_𝑂𝐶_𝑂=𝐿𝐼_𝑂𝐶_𝑂𝑉_𝑂𝐷^′_𝑀<𝑅_𝐼𝑔_𝑚𝑖𝑔_𝑚𝑣, (3) where D_M is the duty-cycle of S_M, 𝐷^′_𝑀 is (1−D_M), and M is the modulator gain. Note that 𝑧_RHP and 𝑓_𝐼.0dB shift to lower frequencies with increasing inductance values, which means that 𝑓_𝑉.0dB must also decrease accordingly, in an ideal case. LPF pole 𝑝_LPF, whose location indicates the lowest frequency at which the current loop is closed, must also be below the worst-case value of 𝑓_𝑉.0dB to ensure there is enough gain for i_L to remain a current source:𝑝_LPF<𝑓_𝑉.0dB|min=𝐷^′_𝑀²𝑉_𝑂2𝜋𝐿𝐼_𝐿. (4) Ultimately, the system responds to a load dump at the speed of the voltage loop, whose bandwidth is 𝑓_𝑉.0dB, allowing switch S_M to cycle multiple times before restoring v_O back to its target window. LPF pole 𝑝_LPF limits the extent to which i_L naturally responds to a load dump by allowing moderate-to-high frequency ac error-correcting signals through the current loop. In other words, the current loop limits (while attempting to regulate) the rising and falling rates of average i_L below i_L’s maximum possible slew-rates of V_IN/L and (v_O – V_IN)/L. Because 𝑓_𝑉.0dB and 𝑝_LPFboth decrease with increasing L, with the former also decreasing with decreasing C_O, the worst-case LC combination, from the perspective of stability, occurs at the highest L and lowest C_O, the condition for which gains R_Ig_miR_S and g_mvR_S and pole 𝑝_LPF are adjusted and transient-response performance over the entire LC filter range is sacrificed.

3. Proposed Dual-Mode ΣΔ Controller IC

The proposed ΣΔ boost controller IC in Figure 4 overcomes the transient-response degradation associated with the worst-case LC combination by bypassing the main voltage loop (and its 𝑓_𝑉.0dB) with a fast (and lower low-frequency loop gain) feed-forward path only during transient events. The stability requirements of the main loop set the acceptable 𝑅_ESRLC range for the system while the high-bandwidth bypass path allows the system to respond in one cycle at the maximum possible inductor current slew rate, the response of which is similar to ΣΔ buck converters. The transient improvement is achieved on chip (i.e., without an off-chip frequency compensation circuit) and without sacrificing LC compliance.

Figure 4 

Simplified schematic of the proposed dual-mode ΣΔ boost converter.

3.1. Steady-State and Bypass Operation

The basic objective of the bypass mode is to override nominal equivalent average inductor current reference 𝐼_𝐿(nom) (𝑣_𝐼.REF/R_I) to a higher value almost instantly only during load dumps and allow the bypass voltage loop to control and limit how much of the extra current in L flows to v_O. Initially, during steady-state conditions, the bypass circuit is inactive and load current i_O and S_M’s average off duty cycle 𝐷^′_𝑀 (i.e., one minus S_M’s average on duty cycle D_M) set the nominal average inductor current 𝐼_𝐿(nom) required to support a given i_O, which is higher than i_O because S_M steers a portion of i_L away from v_O to ground according to D_M:𝐼_𝐿(nom)=𝐼_𝑂𝐷_𝑀′=𝐼_𝑂1−𝐷_𝑀. (5) In the bypass mode, however, independent loops regulate i_L to a value higher than 𝐼_𝐿(nom) and sensed output voltage v_S to 𝑉_REF, as depicted in the equivalent circuit of Figure 5.

Figure 5 

Equivalent circuit of the proposedΣΔconverter in the bypass mode.

The current loop, which modulates switching frequency f_SW and S_M’s duty cycle d_M, has higher bandwidth and appears as a current source for frequencies of interest to the lower bandwidth bypass voltage loop controlling auxiliary switch S_A. In the bypass mode, inductor current i_L is regulated at a value I_PK or V_PK/R_I that is greater than 𝐼_𝐿(nom) (i.e., I_L required to support I_O). This means, unless otherwise limited, average diode current I_D is now higher than I_O, as a result of which C_O recharges quickly. Once v_O is back within the hysteretic window limit of bypass comparator CP_B and about to surpass its upper boundary, CP_B and S_A divert excess current away from 𝐷 through S_A until i_O again discharges v_O to CP_B’s lower window limit. The switching cycle repeats as average inductor current I_L gradually drops back to 𝐼_𝐿(nom), at which point the bypass loop stops switching and S_A remains open. Note as long as I_L exceeds 𝐼_𝐿(nom), the bypass voltage loop, by independently regulating v_O with higher loop gain than the current loop, ensures that the voltage inputs of summing comparator CP_S are virtually short-circuited (i.e., v_S≈𝑉_REF), as shown in Figure 6, allowing CP_S to regulate i_L exclusively.

Figure 6 

Simplified conceptual circuit schematic of the dual-mode ΣΔ converter in bypass mode, as the bypass loop virtually shorts 𝑣𝑆 and 𝑉REF and the current loop regulates 𝑖𝐿 to 𝑣I.REF/𝑅𝐼.

With respect to stability, as already mentioned, the unity-gain frequency of the current loop (𝑓_𝐼.0dB) must exceed that of the bypass voltage loop (𝑓_𝐵.0dB) so the inductor appears as a current source in the voltage loop, eliminating the complex conjugate pair associated with LC in the voltage loop [12]. Because the unity-gain bandwidth of a ΣΔ loop is its switching frequency, S_M’s switching frequency (𝑓_𝐼.0dB) must exceed that of S_A (𝑓_𝐵.0dB). Therefore, since 𝑓_𝐼.0dB depends on the rising and falling rates of i_LR_I as it traverses CP_S’s hysteretic current window H_I,𝑓_𝐼.0dB𝐻=(^𝐼𝑅_𝐼)⁻¹(𝐿𝑉_𝐼𝑁+𝐿𝑉_𝑂−𝑉_𝐼𝑁)⁻¹=𝑉_𝐼𝑁(𝑉_𝑂−𝑉_𝐼𝑁)𝑅_𝐼𝑉_𝑂𝐻_𝐼𝐿 (6) and 𝑓_𝐵.0dB on how fast excess i_D (i.e., 𝐷^′_𝑀I_L – I_D) and I_O charge and discharge output capacitor C_O between CP_B’s hysteretic voltage window H_V,𝑓_𝐵.0dB𝐻=(^𝑉(𝑅₁+𝑅₂)𝑅₂)⁻¹(𝐶_𝑂𝐼_𝑂+𝐶_𝑂(𝐷^′_𝑀𝐼_𝐿−𝐼_𝑂))⁻¹, (7) to force 𝑓_𝐼.0dB to be greater than 𝑓_𝐵.0dB, C_O must exceed 𝐶_𝑂𝐻≥(^𝐼𝐻_𝑉𝐼)(^𝑂𝐿𝑉_𝑂𝑅_𝐼𝐷^′_𝑀𝑅)(²𝑅₁+𝑅₂)≡𝐶_𝑂(min), (8) where the R₁-R₂ divider represents the effect of the resistive feedback factor on H_V and 𝐶_𝑂(min)the minimum stable output capacitance.

3.2. Transient Response and Mode Transition

During a positive load-dump event, when I_O suddenly rises and v_O droops in response, as shown in Figure 7, the dual-mode converter enters its bypass mode, raising i_L to peak value I_PK (or V_PK/R_I) in a single switching cycle of S_M. Subsequently v_O (or v_S) is pulled back to 𝑉_REF (R₁+R₂)/R₂ (or 𝑉_REF) in a single switching cycle of S_A. Transient-detect comparator CP_T in Figure 4 perceives the load dump and engages the bypass mode by sensing when v_S drops below 𝑉_REF by a preset threshold value of Δ𝑉_𝐵𝑃 (e.g., 2.5% of 𝑉_REF) (after the delay the comparator requires to switch: t_d). Then, CP_T clamps 𝑣_𝐼.REF to peak voltage V_PK, the value of which sets the maximum current the circuit can drive. Switch S_M therefore remains closed (𝑡_{𝑡.𝑀(on)}) until i_L reaches V_PK/R_I (I_PK), the new value of 𝑣_𝐼.REF/R_I. After S_M resumes switching and regulating i_L about I_PK, S_A remains open and allows all diode current i_D to flow to v_O until C_O recharges to (𝑉_REF+H_V/2)⋅(R₁+R₂)/R₂. Beyond this point, CP_B and S_A regulate v_S about 𝑉_REF by switching S_A, in other words, by steering excess inductor current away from C_O.

Figure 7 

Transient-response performance when presented with fast load-steps (positive and negative).

Ultimately, output voltage v_O droops in response to load dump Δi_O until 𝑖_𝐿 reaches I_PK. First, excess current Δi_O discharges C_O during delay t_d while v_S reaches 𝑉_REF−Δ𝑉_𝐵𝑃. Then, while S_M raises i_L from 𝑖_𝐿(avg) (or 𝑉_REF/R_I or 𝐼_𝐿(nom)1) to I_PK(or V_PK/R_I), i_D is zero and full load current I_O discharges C_O, yielding a total variation (Δv_O) ofΔ𝑣_𝑂=Δ𝑉_𝐵𝑃𝐼+(^𝑂𝐶_𝑂)𝑡_{𝑡.𝑀(on)}=Δ𝑉_𝐵𝑃𝐼+(^𝑂𝐶_𝑂)[(𝐼_𝑃𝐾−𝐼_𝐿(nom)1)𝐿𝑉_𝐼𝑁]=Δ𝑉_𝐵𝑃𝐼+(^𝑂𝐶_𝑂)(𝑉_𝑃𝐾−𝑣_𝐼.REF)𝐿𝑅_𝐼𝑉_𝐼𝑁. (9) Note that the ratio of L and C_O sets the dominant part of Δ𝑣_𝑂.

Once sensed output voltage v_S is within the hysteretic voltage window of CP_B, to transition back to steady state, 𝑖_𝐿(avg) must somehow fall back to whatever value (𝐼_𝐿(nom)) is necessary to sustain I_O, reducing to zero the amount of excess current i_L that bypass comparator CP_B steers away from v_O through S_A. To that end, introducing a series negative offset voltage 𝑉_𝐼.OS, as shown in Figure 8, ensures that i_L is always above its target (i.e., 𝑖_𝐿(avg)is greater than v_𝐼.REF/R_I), forcing the loop to gradually decrease both 𝑖_𝐿(avg) and the excess current. Finally, when i_L is low enough to be able to fully supply i_O, and the excess current (𝐷^′_𝑀I_L–I_O) is zero, the bypass loop stops switching (i.e., disengages), which means that the main voltage loop now regulates v_O via S_M (Figure 4) to its target. In other words, henceforth, 𝑖_𝐿(avg) equals 𝐼_𝐿(nom). Note that the transition is continuous, allowing S_A to stop switching without incurring irregularities in S_M.

Figure 8 

Equivalent converter circuit in bypass mode with added offset voltage 𝑉𝐼.OS to ensure that 𝑣𝐼.REF/𝑅𝐼 is slightly below 𝑖𝐿(avg).

During a negative load dump, when i_O suddenly drops, as also shown in Figure 7, 𝑖_𝐿(avg) automatically exceeds its new steady-state target and v_O rises above its target. As a result, bypass comparator CP_B engages and diverts current away from v_O until v_S again drops to 𝑉_REF–H_V/2 (in one cycle of S_A). The circuit gradually transitions back to steady state in the same manner as described earlier, through 𝑉_𝐼.OS.

4. Experimental Results and Discussion

4.1. IC Design

The proposed dual-mode ΣΔ bypass converter was designed, fabricated, and evaluated using a 0.5𝜇m, 5 V CMOS process. The circuit embodiment of the converter, as shown in Figure 9, employs a differential-signal processing scheme to attenuate the effects of substrate noise on the high-bandwidth ΣΔ loops [10]. For simplicity, series resistor R_I senses i_L with the understanding more power efficient techniques are possible and recommended [13]. Current-sense amplifier A_DI, which monitors the voltage across R_I, includes an internal RC filter that generates differential current reference 𝑣_𝐼.REF. Differential preamplifier A_DV buffers and amplifies sensed output voltage v_S by 5V/V to decrease the effects of offsets and hysteretic window limits in posterior amplifiers and comparators on v_S and v_O (i.e., improve accuracy); A_DV drives differential summing amplifier A_DS, bypass hysteretic comparator CP_B, and transient-detect hysteretic comparator CP_B.

Figure 9 

0.5𝜇m CMOS circuit embodiment of the proposed dual-mode ΣΔ bypass boost converter.

For ease of design and reliability, main, bypass, and transient-detect comparators CP_M, CP_B, and CP_T adopt the same circuit architecture, which is designed to yield a hysteretic window of 140 mV. The bypass threshold voltage (ΔV_BP) is composed of half the comparator hysteretic window plus an additional offset of 50 mV (𝑉_𝑉.OS) that is added between CP_B and CP_T. Differential current-sense amplifier A_DI includes a 40 mV offset voltage (𝑉_𝐼.OS) at its output to ensure i_L is below its target by 𝑉_𝐼.OS/R_I during the bypass mode, to gradually transition back to steady state after a load dump. The designed offsets are sufficiently large to dwarf the transistor mismatch-induced offsets in A_DI, CP_B, and CP_T and ensure that the polarities of 𝑉_𝑉.OS and 𝑉_𝐼.OS remain unchanged across process and temperature corners.

In the absence of deep-N or buried layer isolation structures, the bulk of a single PMOS transistor serving the function of auxiliary switch S_A could not be connected to the highest potential (v_O) because of latch-up concerns. Whenever the switching node flies above v_O following the turn-off of S_M, S_A’s body diode can conduct engaging the parasitic vertical PNP transistor present, channeling considerable current to the substrate. A second PMOS device is therefore added in series to use its reverse-biased body diode to block the foregoing current. And during normal operating conditions, when v_O is higher than V_IN, as the body diode of the first blocks the current of the second.

The proposed ΣΔ controller 0.5𝜇m IC was designed to supply power from a 2.7–4.2 V Li-Ion battery and drive a 0-1 A load at 5V ± 5% with as wide an 𝑅_ESRLC range as possible (0–50 mΩ, 1–30𝜇H, and 1–350𝜇L was achieved). The total silicon surface area the IC occupied was 1.9×2.6 mm (Figure 10). The peak efficiency of the converter was 93% at 0.4A with a biasing quiescent current of 1.5 mA. The total output voltage variation of the converter in response to a 0.1–1A load dump (Δi_O) with 5 mΩ, 5.6 𝜇H, and 53 𝜇F of 𝑅_ESRLC was 200 mV, which constitutes a 4x improvement over its nonbypassed counterpart under similar conditions (800 mV).

Figure 10 

Die photograph and performance summary.

4.2. LC Compliance

The measured 𝑅_ESRLC space for which the converter was stable is 0–50 mΩ, 1–30𝜇H, and 1–350𝜇F, as illustrated in Figure 11. This range was determined by subjecting the converter to 0.1–1A load dumps with 100 nanoseconds rise and fall times. The stability limit was observed as a loss of regulation for the proposedΣΔ converter in the bypass mode, as the bypass loop was no longer able to control the loop, and subharmonic oscillations for the nonbypassed (state-of-the-art) ΣΔ boost converter [14].

Figure 11 

Nominal steady-state snapshot of inductor current 𝑖𝐿 and output voltage 𝑣𝑂 ripples (inset) for the proposed solution and experimental 𝑅ESRLC stability space for both the proposed dual- and state-of-the-art single-mode boost ΣΔ converters.

The stability limits for both converters, with and without the bypass path, are reached when their respective current-loop bandwidths (𝑓_𝐼.0dB) approach their voltage-loop counterparts (𝑓_𝐵.0dB and 𝑓_𝑉.0dB), as that is when L ceases to be a current source for the voltage loop, be the main loop, or the bypass loop. As a result, because 𝑓_𝑉.0dB and 𝑓_𝐵.0dB increase with decreasing C_O and increasing I_O and 𝑓_𝐼.0dB and RHP zero 𝑧_RHP decrease with increasing L and decreasing V_IN, the highest L-I_O(30 𝜇H–1A) and lowest C_O-V_IN (12 𝜇F-2.7 V) combination constitutes worst-case conditions. Since 𝑅_ESRessentially introduces a left-half plane zero in the voltage loop, increasing 𝑅_ESRalso increases 𝑓_𝑉.0dB and 𝑓_𝐵.0dB, which means that the above-mentioned limits along with the highest 𝑅_ESRvalue (50 mΩ) describe the worst-case stability point of the converter. In other words, 𝐶_𝑂(min) increases with increasing L, I_O, and 𝑅_ESRand decreasing V_IN.

The maximum capacitance was limited to 350 𝜇F as a practical limit for the intended portable application space (the circuit is stable at higher C_O values). Similarly, the maximum 𝑅_ESRvalue was limited to 50 mΩ to keep the output voltage ripple acceptably low under a 1 A load. Under these conditions and constraints, the stability spaces for the proposed and the state-of-the-art converters are approximately equal in “volume.”

4.3. Transient Load-Dump Performance

As shown in Figure 12(a), the transient-response variation of 𝑣_O (Δ𝑣_𝑂) in response to 0.1–1A load dumps (Δ𝑖_𝑂) with 100 nanoseconds rise and fall times under 2.7 V, 5.6 𝜇H, 53𝜇F, and 5 mΩ of 𝑉_𝐼𝑁, L, 𝐶_𝑂, and 𝑅_ESRwas 200 mV for the proposed dual-mode scheme and 800 mV for its single-mode state-of-the-art counterpart. While the proposed converter responds by increasing 𝑖_𝐿 above its target (to 𝐼_𝑃𝐾 or 𝑉_𝑃𝐾/𝑅_𝐼) in one switching cycle of 𝑆_𝑀, the state-of-the-art circuit increases𝑖_𝐿 gradually, pulling𝑣_𝑂 back to regulation in several cycles of 𝑆_𝑀, which is why the proposed solution exhibits a fourfold improvement over its predecessor. In a negative load-step (Figure 12(b)), while the excess inductor current is immediately bypassed by switch 𝑆_𝐴 in the proposed converter keeping the output voltage overshoot low (<75 mV), the excess inductor energy causes a large voltage overshoot (600 mV) in the state-of-the-art converter.

(a)

(b)

Figure 12 

Measured transient performance of the proposed dual-mode and state-of-the-art single-mode ΣΔboost converters in response to (a) 0.1–1 A and (b) 1–0.1 A load steps.

Decreasing (increasing) L increases (decreases) the rate at which i_L responds to a load dump, as shown in Figure 13, thereby decreasing (increasing) the time 𝑣_𝑂 slews (reducing Δ𝑣_𝑂). Similarly, increasing (decreasing) 𝐶_𝑂 decreases (increases) 𝑣_𝑂’s droop rate in response to a load dump (Figure 14). Note that increasing (decreasing) 𝐶_𝑂 also increases (decreases) the delay time between the load step and the onset of bypass threshold voltage Δ𝑉_𝐵𝑃(𝑡_𝑑)(Figure 7), which is why the onset of 𝑖_𝐿 rising shifts with 𝐶_𝑂.

Figure 13 

Measured effects of L on the transient performance of the proposed dual-mode ΣΔ bypass boost in response to 0.1–1 A load dumps, 𝐶𝑂=53𝜇F.

Figure 14 

Measured effects of CO on the transient performance of the proposed dual-mode ΣΔ bypass boost converter in response to 0.1–1 A load dumps.

Although transient-response performance for the proposed dual-mode scheme improves with decreasing L, the same is not true for the single-mode converter whose 𝑖_𝐿 response time is limited by the bandwidth of the loop, not L’s slew rate. As a result, as illustrated in Figure 15, the percentage improvement that the dual-mode enjoys over its single-mode counterpart increases with decreasing L: 6- and 1.43-fold improvement at 1𝜇H–36𝜇F and 30𝜇H–36𝜇F, respectively.

Figure 15 

Measured transient output voltage variation Δ𝑣𝑂 under various LC combinations in response to 0.1–1 A load dumps (Δ𝑖𝑂) for the proposed dual-mode and state-of-the-art single-mode ΣΔ converters.

Increasing 𝐶_𝑂 decreases v_O’s transient droop in both converter cases, except that bypass threshold voltage ΔV_BP effectively limits the extent to which a larger 𝐶_𝑂 decreases Δ𝑣_𝑂 in the proposed scheme. In the limit, increasing 𝐶_𝑂 to such an extent that Δ𝑣_𝑂 is less than Δ𝑉_𝐵𝑃 would prevent the bypass mode from ever engaging. As a result, the performance improvement in Δ𝑣_𝑂 is lower between the proposed and state-of-the-art solutions at higher 𝐶_𝑂 values: Δ𝑣_𝑂 for the proposed and state of the art asymptotically converge as 𝐶_𝑂 increases.

4.4. Mode Transition

Figures 16 and 17 illustrate how the proposed dual-mode ΣΔ bypass boost converter transitions from steady state to bypass mode and back in response to positive and negative 0.1–0.6A load dumps with an LC combination of 15𝜇H and 53 𝜇F. As designed, the bypass mode ripple is larger at ±70 mV (±(𝐻_𝑉/2)⋅(𝑅₁+𝑅₂)/(𝑅₂𝐴_𝐷𝑉) ≈±140 mV/2) or ±1.4% than the steady-state counterpart, which is at ±15 mV or ±0.3%. During a positive load dump (Figure 16), when i_O suddenly rises, a load-induced drop in 𝑣_𝑂 exceeding the Δ𝑉_𝐵𝑃 limit engages the bypass mode and increases 𝑖_𝐿 to 2.5 A (𝐼_𝑃𝐾) in one switching cycle of 𝑆_𝑀. As determined by offset V_𝐼.OS, the circuit then takes approximately 2.5 ms to gradually decrease 𝑖_𝐿 back to its new target of roughly 1.3A, at which point𝑆_𝐴 stops switching and the converter is back in steady state. During a negative load dump (Figure 17), 𝑖_𝐿 is automatically above its target and 𝑆_𝐴 consequently starts diverting some of 𝑖_𝐿 back to 𝑉_𝐼𝑁 almost immediately, until 2.5 ms later, when 𝑖_𝐿 drops to its new target.

Figure 16 

Measured steady state to bypass and back transitions in response to positive 0.1–0.6 A load dumps (positive Δ𝑖𝑂).

Figure 17 

Measured steady state to bypass and back transitions in response to negative 0.6–0.1 A load dumps (negative Δ𝑖𝑂).

The main drawbacks of the auxiliary bypass path are the silicon real estate, power, and switching noise associated with power switch 𝑆_𝐴. The latter two shortcomings, however, are more often than not inconsequential because they only occur during transient events, which are typically sporadic, short, and seldom occur without significantly affecting the steady-state power efficiency (Figure 18). The prominent disadvantage of the proposed solution is therefore additional silicon real estate for𝑆_𝐴 because it carries substantial current. The transient-performance benefits of 𝑆_𝐴 and the bypass path that drives it, however, offset this cost.

Figure 18 

Measured steady-state efficiency Vs. Load current IO for the proposed converter.

5. Conclusion

A dual-mode ΣΔ bypass boost dc-dc controller 0.5𝜇m CMOS IC that is stable for an 𝑅_ESRLC filter range of 0–50 mΩ, 1–30 𝜇H, and 1–350 𝜇F and responds to positive and negative load dumps in one switching cycle has been proposed, designed, fabricated, and evaluated. The driving feature of the foregoing solution is a robust on-chip (i.e., smooth transitioning) ΣΔ bypass path that responds only during transient load dumps. While the converter increases inductor current i_L in one switching cycle in response to a sudden rise in load current i_O and uses it to quickly slew output capacitor C_O back to its target, it also limits how much of i_L flows to 𝐶_𝑂 in the case of a negative load dump, when 𝑖_𝑂 drops, limiting the total transient variation of output voltage 𝑣_𝑂 and therefore improving accuracy performance. The transient-response benefits of the proposed scheme, as compared to state-of-the-art single-mode ΣΔ converters, are the highest at low values of L (e.g., 6x at 1𝜇H and 1.41x or 40% improvement at 30𝜇H) because L limits how fast 𝑖_𝐿 rises and falls to its targets. The main drawback of the proposed technique is the additional silicon real estate required for auxiliary power switch 𝑆_𝐴, which is partially (and often completely) offset by its improved accuracy performance. In summary, the proposed dual-mode ΣΔ bypass boost converter is fast, widely LC compliant (robust), and easily implementable.

Acknowledgment

This work was supported by Texas Instruments.