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Advances in Power Electronics
Volume 2011 (2011), Article ID 713250, 13 pages
http://dx.doi.org/10.1155/2011/713250
Research Article

Primary Droop Current-Sharing Control of the Parallel DC/DC Converters System considering Output Cable Resistance

Department of Electrical Engineering, Ching Yun University of Technology, 229, Chien-Hsin Road, Jung-Li 320, Taiwan

Received 7 December 2010; Accepted 9 February 2011

Academic Editor: Francesco Profumo

Copyright © 2011 J. B. Wang. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Abstract

This paper presents a primary droop current-sharing controller that can integrate into voltage feedback controller and, thus, provides a low-cost and simple solution for parallel DC/DC converters system. From the equivalent small-signal model, a two-port network was adapted to describe the output and control variables for designing voltage and droop current-sharing loops. From the analysis results, the designed primary droop current-sharing controller will not affect the original voltage loop gain profile to let the DC/DC converter preserve desire control performance. After designing a stable DC/DC converter with primary droop current-sharing control, the stability of the interconnected parallel DC/DC converters system was studied. When the cable resistance is reduced, when the cable resistance is reduced, the interconnected system might be unstable. Finally, some simulation and experimental results demonstrated the effectiveness of the proposed controller in a prototype parallel DC/DC converters system.

1. Introduction

In general, the server power system infrastructure consists of frond end AC/DC converters to build up high DC voltage and DC/DC converters to provide power to downstream load. The AC/DC converter uses power factor correction control to let the input line current meet the current harmonic specification; furthermore, the second-stage DC/DC converters and the interconnected cables construct a DC-distributed power system. A DC power system consists of many standard DC/DC converters through interconnected cables or copper buses in series or parallel to obtain desire output voltage, current, and power [14]. The structures of the interconnected DC power system have four topologies, that is, input series output series, input series output parallel, input parallel output series, and input parallel output series [2, 4]. The series structure can obtain high output voltage or withstand high input voltage; the kernel of the control strategy is to achieve voltage balance operation among the DC/DC converters. As to the parallel operation, high output current is the major advantage. However, the equal current-sharing control among each of DC/DC converters is the key performance index. In the server power system infrastructure, the parallel DC/DC converters system plays the key role to provide low voltage and high output current capability through the delicate designed interconnected system.

In order to obtain equal current-sharing control in the parallel DC/DC converters system, the current-sharing control should be designed. The most prevailing current-sharing control scheme is the active current-sharing control scheme, especially, the master slave and average current-sharing controls [510]. The literature [6, 7] provides the key theoretical study in the master slave and average current-sharing controls. However, the control system analysis of the droop current-sharing control seems to have little study. Most of the investigations focused on the steady-state droop voltage characteristics [1118]. In addition, the interconnection of the DC/DC converters to form the parallel DC power system requires extra cable wires or copper buses. The study depicted suitable cable resistance can improve the stability of the parallel DC/DC converters system [19]. Furthermore, the common mode stability problem caused by the interconnected and system impedances was found in the paper [7]. The results showed the analysis and design method to obtain a stable interconnected system is to design a stable DC/DC converter and then to analysis the stability of the interconnected subsystem [20]. Finally, if the aforementioned analysis is stable, then the whole DC power system is also stable.

The major purposes of this paper are to design a controller that integrates the voltage and droop current-sharing controllers and to investigate the effects of the output cable resistance to the stability of the interconnected system. Firstly, the small signal model of the buck derived converter was derived in term of the two-port network. From the model reveals the cross-coupling effect was caused from the primary droop current-sharing control path. In order to preserve the voltage loop gain profile, the droop controller was proposed to reduce the parameter uncertainty of the DC/DC converter. After designing a stable DC/DC converter primary with droop current-sharing control, the final interconnected system was analyzed. This system consists of many cable wires to parallel connect the output voltages of the DC/DC converters to the system load. Using the circuit theory to analyze this interconnected system found the cable resistance might affect system stability. Through the investigation of a simple interconnected system, the phase margin will reduce when the cable resistance was reduced. In addition, the Spice-based circuit simulation further confirmed this phenomenon. Finally, the design methods of the droop voltage characteristics and controllers are provided in the appendix. Furthermore, some simulations and experimental results are used to demonstrate the aforementioned findings.

2. Modeling of a Parallel DC/DC Converters System with Primary Droop Current-Sharing Control

Figure 1(a) shows a parallel DC/DC converters system with primary droop current-sharing control which consists of 𝑁 DC/DC converters, and the symbol 𝑖 denotes the 𝑖th DC/DC converter for 𝑖=1 to 𝑁. The interconnection of the DC/DC converters system to load 𝑧𝐿 is modeled as a resistor 𝑟𝑤𝑖 for 𝑖=1 to 𝑁. In addition, the notations 𝑉𝑜𝑖 and 𝑉𝑜 denote the output voltage of the 𝑖th DC/DC converter and actual load voltage. In order to clarify the voltage and primary droop current-sharing controllers, Figure 1(b) details the actual circuits implementation of the 𝑖th DC/DC converter, which is an interleaved dual switch forward converter (IDSFC) with one output inductor. Furthermore, the symbols 𝑉ref𝑖, 𝑉𝑖, 𝑛, 𝐼𝑜𝑖, and 𝐼𝑖𝑖 denote reference command setting, input voltage, transformer turn ratio, output current, and primary input current, respectively. The voltage controller integrates 𝐺𝑐1(𝑠) and 𝐺𝑐2(𝑠) controllers with the 𝐺dr(𝑠) droop controller using a simple analog controller and thus provides a low-cost solution. The meanings of the controllers parameters can be comprehended by their notations. The low-pass filter 𝐺𝑓(𝑠) senses the primary input current and generates the designed droop voltage command 𝑉dr with respect to different load currents.

fig1
Figure 1: (a) The parallel DC/DC converters system; (b) the interleaved dual switch forward converter with primary droop current-sharing control.

Figure 2(a) shows the equivalent small signal circuits of the 𝑖th DC/DC converter, where the nominal duty ratio, equivalent secondary voltage, and equivalent series resistances of output capacitor and inductor are 𝐷, 𝑉𝑔, 𝑟𝑐, and 𝑟𝐿, respectively, and 𝑉𝑔=𝑉𝑖/𝑛 [21]. Furthermore, the lower case symbols 𝑣𝑖, 𝑑𝑖, 𝑣𝑔, 𝑖𝑔𝑖, 𝑖𝑖𝑖, and 𝑖𝑜𝑖 denote the small signal variables of the aforementioned uppercase notations. For a 𝑁 parallel DC/DC converters system, the output current of the 𝑖th DC/DC converter 𝐼𝑜𝑖 equals to 𝐼𝑜/𝑁 in an equal current-sharing operating condition, where 𝐼𝑜 is the total load current, and, thus, the equivalent load resistance of each DC/DC converter is 𝑅𝑛=𝑉𝑜/𝐼𝑜𝑖 for small signal analysis. The small signal model of the converter in Figure 2(b) shows that droop current-sharing control via sensing primary input current contains an extra current source, that is, 𝐼𝑜𝑖𝑑𝑖. This current source shows an extra coupling effect between input current 𝑖𝑖𝑖 and duty ratio 𝑑𝑖. Neglecting the perturbation of the input voltage, the small signal model of the 𝑖th DC/DC converter is similar to a two-port network as shown in Figure 2(b) to be 𝑣𝑜𝑖𝑖𝑖𝑖=𝐻𝑖𝑧𝑜𝑖𝐹𝑑𝑖𝐴𝑖𝑖𝑑𝑖𝑖𝑜𝑖,𝐻𝑖=𝑣𝑜𝑖𝑑𝑖||||𝑖𝑜𝑖=0,𝑧𝑜𝑖=𝑣𝑜𝑖𝑖𝑜𝑖||||𝑑𝑖𝐹=0,𝑑𝑖=𝑖𝑖𝑖𝑑𝑖||||𝑖𝑜𝑖=0,𝐴𝑖𝑖=𝑖𝑖𝑖𝑖𝑜𝑖||||𝑑𝑖=0,(1) where input variables are 𝑑𝑖 and 𝑖𝑜𝑖, and output variables are denoted as 𝑣𝑜𝑖 and 𝑖𝑖𝑖, respectively. The key transfer functions used for analysis latterly list in the appendix. The detailed design and analysis are introduced as follow.

fig2
Figure 2: (a) The small signal model of the IDSFC; (b) the equivalent two port network.

3. Parallel DC/DC Converters System Analysis and Design

3.1. Voltage and Droop Current-Sharing Loops Design

From Figure 2(b), the 𝑖th DC/DC converter includes the voltage feedback, and primary droop current-sharing controllers are shown in Figure 3(a); furthermore, Figure 3(b) is its equivalent control block diagram and suitable for control system analysis via signal flow method. As a result, the total loop gain of the 𝑖th DC/DC converter is 𝑇loop=𝑇𝑣+𝑇dr,𝑇(2)𝑣=𝐺𝑐1𝐺𝑐2𝐾𝐻𝑖𝑇,(3)dr=𝐾𝐹𝑑𝑖𝐺𝑓𝐺dr𝐺𝑐1,(4) where 𝑇𝑣 and 𝑇dr denote voltage and droop current-sharing loop gains, respectively. Let the droop current-sharing controller design as 𝐺dr=𝑘𝑑𝐺𝑐2.(5) The gain constant 𝑘𝑑 can deduce from Figure 1(b) to be 𝑅2/𝑅3. Substituting (5) into (4), the total loop gain can be expressed as 𝑇loop=𝑇𝑣𝑘(1+Δ𝑊),Δ𝑊=𝑑𝐺𝑓𝐹𝑑𝑖𝐻𝑖.(6) In order to preserve the original voltage loop gain profile and not to be affected by the droop current-sharing loop, the transfer function Δ𝑊 must meet the following criterion: Δ𝑊1.(7) After manipulating the transfer function Δ𝑊, the denominators of the transfer functions 𝐻𝑖 and 𝐹𝑑𝑖 can cancel so the resonant peak of the transfer function Δ𝑊 will not occur. Furthermore, the droop gain constant 𝑘𝑑 and transformer turn ratio also contribute to let Δ𝑊 less than 1. Properly design the low-pass filter 𝐺𝑓 to let Δ𝑊 be proper, and the effect of the transfer function Δ𝑊 to voltage loop gain could be small. As a result, the transfer function Δ𝑊 can be regarded as parameter uncertainty of the plant. To reduce parameter uncertainty of the plant, the simple approach is to increase the gain margin of the DC/DC converter. If the gain margin is greater than 10 dB, the effect of the parameter variations in modeling error can reduce [6]. The great benefit of using the design droop controller depicted in (5) is that the voltage and droop current-sharing controllers can integrate and implement in a single operational amplifier as shown in Figure 1(b). The voltage controller shown in Figure 1(b) is a simple lead-lag controller 𝐺𝑐(𝑠) which consists of the controllers 𝐺𝑐1(𝑠) and 𝐺𝑐2(𝑠), and can be expressed as 𝐺𝑐(𝑠)=𝐺𝑐1(𝑠)𝐺𝑐2=(𝑠)𝑠/𝜔𝑧1+1𝑠/𝜔𝑧2+1𝑠/𝜔𝑜1𝑠/𝜔𝑝1+1𝑠/𝜔𝑝2,+1(8) where the poles and zeros of the voltage controller are 𝜔𝑜1, 𝜔𝑝1, 𝜔𝑝2, 𝜔𝑧1, and 𝜔𝑧2, respectively, and might be comprehended from (8). A simple pole placement method suggested in the literature [22], and the desired total loop gain can be approximated as 𝑇loop=𝑇𝑣1(1+Δ𝑊)𝑠/𝜔𝑜𝑠/𝜔𝑝2+1,(9) where the pole 𝜔𝑜 designs to obtain desired bandwidth and phase margin; furthermore, the 𝜔𝑝2 filters out the switching noise. The detail parameters of the integrated controller are listed in the appendix.

fig3
Figure 3: (a) The control block diagram of the 𝑖th DC/DC converter in parallel DC/DC converters system; (b) the corresponding block diagram of the 𝑖th DC/DC converter.
3.2. Interconnected System Analysis

In general, the stable DC/DC converter can be designed by aforementioned pole placement scheme shown in (8). When a lot of stable DC/DC converters are paralleling operation, the interconnection of the DC/DC converters to actual load forms an interconnected system. In the following analysis, the Thevenin theorem and signal flow method were used. From Figure 3(b), the feedback output impedance of the DC/DC converter is 𝑧of𝑖=𝐴𝑖𝑖𝐺𝑓𝐺dr𝐺𝑐1𝐾𝐻𝑖+𝑧𝑜𝑖1+𝐺𝑓𝐺dr𝐺𝑐1𝐾𝐹𝑑𝑖1+𝑇𝑣+𝑇dr𝑘𝑑𝐺𝑓𝐴𝑖𝑖𝑇𝑣+𝑧𝑜𝑖𝑇dr1+𝑇𝑣+𝑇dr.(10) Obviously, the feedback output impedance of the DC/DC converter with primary droop current-sharing control is discrepant to original feedback output impedance. In fact, the primary droop current-sharing loop affects the feedback output impedance. Furthermore, the transfer function from reference command setting 𝑣ref𝑖 to output voltage 𝑣𝑜𝑖 can be deduced as 𝐹𝑖𝑣(𝑠)=𝑜𝑖𝑣ref𝑖=𝐺𝑐1𝐾𝐻𝑖1+𝑇loop.(11) Then, the equivalent Thevenin small signal model of the parallel DC/DC converters system is showed in Figure 4. Using node analysis at output node, the relations of the output current 𝑖𝑜𝑖 to reference command 𝑣ref𝑖 of each DC/DC converter for 𝑖=1,,𝑁 are 𝐹1𝑣ref1𝐹2𝑣ref2𝐹𝑁𝑣ref𝑁=𝑧𝐿+𝑟𝑤1+𝑧of1𝑧𝐿𝑧𝐿𝑧𝐿𝑧𝐿+𝑟𝑤2+𝑧of2𝑧𝐿𝑧𝐿𝑧𝐿𝑧𝐿+𝑟𝑤𝑁+𝑧of𝑁×𝑖𝑜1𝑖𝑜2𝑖𝑜𝑁.(12) The aforementioned matrix in (12) is nonsingular so its inverse matrix exists. Using matrix inversion formula ((𝐷𝐶𝐸)1=𝐷1+𝐷1𝐶(𝐼𝐸𝐷1𝐶)1𝐸𝐷1), the output current 𝑖𝑜𝑖 is 𝑖𝑜1𝑖𝑜2𝑖𝑜𝑁=𝑧11000𝑧21000𝑧𝑁11Δ𝑧𝐿𝑧21𝑧𝐿𝑧1𝑧2𝑧𝐿𝑧1𝑧𝑁𝑧𝐿𝑧1𝑧2𝑧𝐿𝑧22𝑧𝐿𝑧2𝑧𝑁𝑧𝐿𝑧1𝑧𝑁𝑧𝐿𝑧2𝑧𝑁𝑧𝐿𝑧2𝑁×𝐹1𝑣ref1𝐹2𝑣ref2𝐹𝑁𝑣ref𝑁,(13) where 𝑧𝑖=𝑟𝑤𝑖+𝑧of𝑖,Δ=1+𝑁𝑗=1𝑧𝐿𝑧𝑗.(14) If the parameters of the DC/DC converters are identical and symmetric layout interconnected system is designed, that is, the cable resistance is identical. In this condition, The reference command setting 𝑣ref𝑖 of the 𝑖th DC/DC converter is perturbed by ̂𝑣ref𝑖, and the resulted output current perturbation ̂𝑖𝑜𝑗 for 𝑗=1,,𝑁 is ̂𝑖𝑜𝑗=𝑧+(𝑁1)𝑧𝐿𝑧𝑧+𝑁𝑧𝐿̂𝑣ref𝑖𝑧,𝑗=𝑖,𝐿𝑧𝑧+𝑁𝑧𝐿̂𝑣ref𝑖,𝑗𝑖,𝑗=1,,𝑁,(15) where 𝑧𝑗=𝑧, 𝑗=1,,𝑁. In general, the transfer function 𝐹𝑖 is stable, and if the zeros of the denominator of (14) locate at on left half plane, then the parallel DC/DC converters system is stable. The aforementioned method can be applied to other DC/DC converters like boost converter for example.

713250.fig.004
Figure 4: The Thevenin equivalent parallel DC/DC converters system.

4. Simulation and Experiment

Obviously, from (12) to (15), it is very difficult to find the effect of the output cable resistance to system stability. In order to clarify this, an interconnected system equips with two DC/DC converters is analyzed in detail. From Figure 3, one can construct the control system block diagram of the interconnected system as shown in Figure 5(a). Using (9) to (13), the cross coupling effects of the interconnected system depicts in Figure 5(b). The loop gain of the interconnected system is 𝑇𝑧loop=𝑧of𝑖𝑦11+𝑧of𝑗𝑦22𝑧of𝑖𝑦12𝑧of𝑗𝑦21+𝑧of𝑖𝑦11𝑧of𝑗𝑦22,(16) where 𝑦11=𝑧𝐿+𝑟𝑤𝑗Δ𝑘,𝑦22=𝑧𝐿+𝑟𝑤𝑖Δ𝑘,𝑦12=𝑦21𝑧=𝐿Δ𝑘,Δ𝑘=𝑧𝐿𝑟𝑤𝑖+𝑧𝐿𝑟𝑤𝑗+𝑟𝑤𝑖𝑟𝑤𝑗.(17) If the parameters of the DC/DC converters are identical and symmetric layout of the interconnected system is designed, (16) can be deuced as 𝑇𝑧loop=𝑧of𝑧of+2𝑧𝐿+2𝑟𝑤Δ𝑘.(18) Substituting the parameters of the IDSFC into the transfer functions 𝐹𝑑𝑖 and 𝐴𝑖𝑖, the resulted frequency responses are demonstrated in Figure 6. It shows the magnitude of the transfer function 𝐹𝑑𝑖 is always above 0 dB due to the extra current source in the small signal model. In addition, the profile of the transfer function 𝐴𝑖𝑖 is similar to the transfer function 𝐻𝑖 with lower gain. Figure 7 depicts the voltage, droop current sharing, and total loop gains and the parameter uncertainty Δ𝑊. One may find Δ𝑊 is –9.91 dB at 40.9 KHz and meets the criterion (7) so the effect of the parameter uncertainty is minimized. Therefore, the profiles of the three loop gains are quite similar with different offset. Using the proposed design droop controller in (5), the total loop gain is not affected by the primary droop current-sharing control significantly. The gain and phase margins of the DC/DC converter can be preserved and gained a stable operation. Figure 8 shows the discrepancy of the open-loop and feedback output impedances. It is interesting to find that the feedback output impedance 𝑧of𝑖 is greater than output impedance 𝑧𝑜𝑖 in low frequency range. However, the feedback output impedance 𝑧of𝑖 is rolled off as frequency increased and does not have resonant peak phenomenon. In order to clarify the effects of the output cable resistance to stability, two different cable resistances were simulated in the interconnected system loop gain as shown in Figure 9. When the cable resistance is reduced from 1 mΩ to 0.1 mΩ, the magnitude of the interconnected system loop gain 𝑇𝑧loop is shifted up and leads to reducing phase margin of the system. From the simulation results, the magnitude and phase were not affected either resistance load or paralleling extra 10000 μF capacitance load. In this simulation case, the phase margin is 70° with 𝑟𝑤𝑖=1 mΩ, but when the cable resistance was reduced to 0.1 mΩ, the phase margin is almost vanishing. In order to further find the effects of the output cable resistance, a Spice-based simulation was carried out via Simetrix/Simplis. Figure 10 shows the output current response of the step referent command disturbance in the 1 mΩ and 0.1 mΩ cases. Figure 9(a) depicts the output currents can subside back into equal current-sharing control in 1 mΩ cable resistance case; unfortunately, Figure 10(b) shows the unstable operation via 0.1 mΩ cable resistance. This conforms the previous comments that a large cable resistance can improve the system stability [19].

fig5
Figure 5: The parallel DC/DC converters system with 𝑁=2 interconnected system: (a) detail control block diagram and (b) simplified diagram.
fig6
Figure 6: The frequency responses of the 𝐹𝑑𝑖 and 𝐴𝑖𝑖 transfer functions at half load current operation: (a) magnitude; (b) phase.
fig7
Figure 7: The frequency responses of the transfer functions 𝑇𝑣, 𝑇dr, 𝑇𝑣+𝑇dr, and Δ𝑊 at half load current operation: (a) magnitude and (b) phase.
fig8
Figure 8: The frequency responses of the opened- and closed-loop output impedances of the DC/DC converter at half load current operation: (a) magnitude and (b) phase.
fig9
Figure 9: The frequency responses of the parallel DC/DC converters system with output cable resistances 1 mΩ and 0.1 μΩ at half load current operation: (a) magnitude and (b) phase.
fig10
Figure 10: The step reference command disturbance of the parallel DC/DC converters system with different output cable resistances at full-load current operation: (a) 1 mΩ and (b) 0.1 μΩ.

After the simulations have demonstrated the performance of the proposed integrated controller for voltage and droop current-sharing control, the paralleled DC/DC converter system with 𝑁=2 was implemented. Furthermore, The PWM IC UC3525 was used to generate two-phase PWM pulses to control IDSFC as shown in Figure 1(b). Figure 11(a) shows the measured primary currents and MOSFET drain to source voltage waveforms for referent. It shows the primary currents of the two forward converters are in balance operation. Owing to one output inductor scheme, two power trains of the IDFSC have the same primary side current, which reflects from the secondary side inductor current as shown in Figure 11(b). Furthermore, the hot swap operation is also depicted in Figure 11(c), the parallel IDFSCs can achieve equal sharing control. Figure 12 shows the loop gain profiles of the IDFSC, which are similar to the simulation results. It shows the designed IDFSC has at least 45° phase margin, 10 dB gain margin, and 10 KHz bandwidth; therefore, the effects of the parameter uncertainty can reduce significantly. Because the cable length of the prototype IDFSC is 30 cm with 2 mΩ resistance as shown in Figure 13(a), the resulted interconnection system is stable. The physical size of the IDFSC and interconnected system can let the cable length be shorted to 15 cm, and the resulted cable resistance is 1 mΩ as depicted in Figure 13(b). However, it is very difficult to obtain 0.1 mΩ cable resistance in this laboratory prototype interconnected system to demonstrate the unstable operation. Fortunately, from the theory study and simulation verification, the cable resistance will affect system stability.

fig11
Figure 11: The key waveforms of the parallel DC/DC converters system at full-load current operation: (a) primary current and primary MOSFET drain to source voltage of the IDSFC; (b) the current and the input voltage of the output inductor; (c) hot swap operation.
fig12
Figure 12: The measured 𝑇𝑣 and 𝑇𝑣+𝑇dr frequency responses of the IDSFC at full-load current operation: (a) magnitude and (b) phase.
fig13
Figure 13: (a) The photograph of the IDSFC with 2 mΩ output cable resistance; (b) the back plane system with 𝑁=2 and the corresponding connected output cables.

5. Conclusions

An interconnected DC power system consists of DC/DC converters with primary droop current-sharing control was presented in this paper. Using the proposed droop controller will not affect the original design voltage loop gain profile but also can integrate into voltage controller and thus provides a low-cost solution. Furthermore, after a stable DC/DC converter design was achieved, the effect of the cable wire resistances of the interconnected system to stability was also investigated. The results demonstrated that the reduction of the cable resistance will decrease the phase margin of the interconnected system and lead to instability. Properly increasing the cable resistance can improve system stability, but the operating efficiency will reduce. This paper provides a method to evaluate the stability of the interconnected system. Using this method, the engineer can make a tradeoff between system stability and efficiency.

tab1
Table 1
tab2
Table 2

Appendix

(1) The Designed Parameters of the Interleaved Dual-Switch Forward Converter Are as Follows.
(i)Primary side DC bus voltage 𝑉𝑖=385 V.(ii)Primary switching frequency 𝑓𝑠=125 kHz.(iii)Nominal output voltage 𝑉𝑜=12 V.(iv)Nominal output current 𝐼𝑜=66 A.(v)Transformer PQ32/30 𝑁𝑃=20 turns, 𝑁𝑠=1 turn, and 𝑛=20.(vi)Output inductor MS10675 with inductance 𝐿=2μH.(vii)Output capacitance 𝐶=5400μF and esr=4 mΩ.(viii)Nominal duty ratio 𝐷=0.62 in the secondary side of the IDSFC with an output inductor.(ix)The gain of the PWM comparator 𝐾=0.25.

(2) The Key Transfer Functions of the IDFSC
𝑣𝑜𝑖𝑑𝑖=𝐻𝑖𝑉(𝑠)=𝑔𝑅𝑛𝑠𝐶𝑟𝑐+1Δ,𝑖𝑖𝑖𝑑𝑖=𝐹𝑑𝑖𝐼(𝑠)=𝑜𝑖+𝐷𝑉𝑔𝑅𝑆𝐶𝑛+𝑟𝑐+1/Δ𝑛,𝑖𝐿𝑖𝑑𝑖=𝐹𝑑𝑖𝐿𝑖𝑉(𝑠)=𝑔𝑆𝐶𝑅+𝑟𝑐+1Δ,𝑖𝑜𝑖𝑑𝑖=𝐹𝑑𝑖𝑜𝑖𝑉(𝑠)=𝑔𝑆𝐶𝑟𝑐+1Δ,𝑧𝑜𝑖=𝑣𝑜𝑖𝑖𝑜𝑖=𝑅𝑛𝑠𝐶𝑟𝑐+1𝑠𝐿+𝑟𝐿Δ,𝐴𝑖𝑖=𝑖𝑖𝑖𝑖𝑜𝑖=𝐷𝑅𝑛𝑠𝐶𝑟𝑐+1Δ,(A.1) where Δ=𝑠2𝑅𝐿𝐶𝑛+𝑟𝑐𝑅+𝑠𝐿+𝐶𝑛𝑟𝐿+𝑅𝑛𝑟𝑐+𝑟𝐿𝑟𝑐+𝑅𝑛+𝑟𝐿𝑅𝑛+𝑟𝐿𝑠𝜔𝑛2𝑠+2𝜉𝜔𝑛+1,𝑅𝑛𝑟𝐿,𝑟𝑐,𝜔𝑛=1,𝑅𝐿𝐶𝜉=𝑍+𝑛𝑟𝐿+𝑅𝑛𝑟𝑐+𝑟𝐿𝑟𝑐/𝑍2𝑅𝑛+𝑟𝐿,𝑍=𝐿𝐶.(A.2)

(3) Design Procedure of the Steady-State Output Voltage Droop Characteristic
In general, the output voltage droop characteristic of a DC/DC converter depends on output voltage regulation specification with a predetermined design margin. If the maximum, nominal, and minimum output voltages of the regulation range are denoted as 𝑉𝑜𝑖,max, 𝑉𝑜𝑖, and 𝑉𝑜𝑖,min, respectively. From Figure 1(b), the output voltage variation of the 𝑖th DC/DC converter with respect to droop current-sharing control is 𝑉𝑜𝑖,max=𝑉𝑜𝑖+Δ𝑉𝑜𝑖=𝑉ref𝑖𝐾𝑑,𝐼𝑜𝑖=0,(A.3) where 𝑉𝑜𝑖,min=𝑉𝑜𝑖Δ𝑉𝑜𝑖=𝑉ref𝑖𝐾𝑑𝑉dr𝐾𝑐𝑠𝐾𝑑,(A.4)𝐾𝑑=𝑅1𝑅3𝑅1𝑅2+𝑅1𝑅3+𝑅2𝑅3,𝐾𝑐𝑠=𝑅1𝑅2𝑅1𝑅2+𝑅1𝑅3+𝑅2𝑅3.(A.5) Furthermore, the droop voltage 𝑉dr synthesizes from primary current through a low-pass filter, which is proportion to output current, that is, 𝐼𝑖𝑖=𝐷𝐼𝑜𝑖/𝑛. From (A.3) and (A.4), the output voltage deviation Δ𝑉𝑜𝑖 can be expressed in terms of droop voltage as Δ𝑉𝑜𝑖=𝑉dr𝐾𝑐𝑠2𝐾𝑑=𝑘𝑑𝑉dr2.(A.6) For a given output voltage deviation Δ𝑉𝑜𝑖, the design procedure of the output voltage droop characteristics is suggested as follows.(i)Let 𝑅1=𝑘𝑉ref𝑖 and 𝑘>0.(ii)The resistance 𝑅2 can subsequently be determined from the maximum output voltage listed in (A.3), 𝐾𝑑, and 𝑅1.(iii)For a given specification of the output voltage deviation and droop voltage, the resistances 𝑅1 and 𝑅3 can be found from (A.6) and resistance 𝑅1.

(4) Voltage and Primary Droop Current-Sharing Controller
The feedback controllers in Figure 1(b) are 𝐺𝑐1(𝑠)=𝑠/𝜔𝑧1+1𝛼2𝑠𝑠/𝜔𝑝1+1,𝐺𝑐2(𝑠)=𝑠/𝜔𝑧2+1𝐾2𝑠/𝜔𝑝2+1,(A.7) where 𝜔𝑝1=1𝐶23𝑅5,𝜔𝑝2=1𝐶1𝑅4,𝜔𝑧1=1𝐶2𝑅5,𝜔𝑧2=1𝐶1𝑅2+𝑅4,𝛼2=𝐶2+𝐶3,𝐶23=𝐶2𝐶3𝐶2+𝐶3,𝐾2=𝑅2,𝜔𝑜1=1𝐾2𝛼2.(A.8)(i)The design poles and zeros of the controller 𝐺𝑐1(𝑠), 𝐺𝑐2(𝑠), and 𝐺dr(𝑠) can let the DC/DC converter have at least 45° phase margin, 10 dB gain margin, and 10 KHz bandwidth 𝜔0=66845rad/sec,𝜔𝑝1𝜔=49019.6rad/sec,𝑝2=212765.95rad/sec,𝜔𝑧1𝜔=4456.33rad/sec,𝑧2=20263.24rad/sec.(A.9)(ii)Circuit parameters of the controller 𝐺𝑐1(𝑠), 𝐺𝑐2(𝑠), and 𝐺dr(𝑠); (see Table 1).

Note
(1) Using the nearest commercial parts instead of the estimated parameters.

(5) Low-Pass Filter 𝐺𝑓(𝑠)
𝐺𝑓=𝑘(𝑠)𝑓𝑠2𝑅𝑓1𝑅𝑓2𝐶𝑓1𝐶𝑓2𝑅+𝑠𝑓1𝐶𝑓1+𝐶𝑓2+𝑅𝑓2𝐶𝑓2.+1(A.10) (see Table 2).

Acknowledgment

The authors thank the National Science Council of Taiwan for supporting the research project: NSC99-2221-E231-036.

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