- About this Journal ·
- Abstracting and Indexing ·
- Aims and Scope ·
- Article Processing Charges ·
- Author Guidelines ·
- Bibliographic Information ·
- Citations to this Journal ·
- Contact Information ·
- Editorial Board ·
- Editorial Workflow ·
- Free eTOC Alerts ·
- Publication Ethics ·
- Recently Accepted Articles ·
- Reviewers Acknowledgment ·
- Submit a Manuscript ·
- Subscription Information ·
- Table of Contents
Advances in Power Electronics
Volume 2012 (2012), Article ID 286861, 9 pages
Controller Design Considerations for ACM APFC Systems
Department of Electrical Engineering and Computer Science, University of California, Irvine, CA 92697, USA
Received 27 February 2012; Revised 6 August 2012; Accepted 7 August 2012
Academic Editor: C. M. Liaw
Copyright © 2012 Alexander Abramovitz. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.
This paper is concerned with performance of the current shaping network in Average Current Mode (ACM) Active Power Factor Correction (APFC) systems. Theoretical expressions for the ripple components are derived. Then, ripple interaction and impact on the current loop reference signal are investigated. A modification of the controller network is suggested that results in an improved Total Harmonic Distortion (THD). Design guidelines are suggested. The theoretical predictions were validated by simulation.
Over the past few years, a variety of current shaping methodologies were developed for Active Power Factor Correction (APFC) [1–3]. Each approach undertaken is a compromise in between the performance indexes and the circuit complexity and cost. The Critical Conduction Mode (CrCM) APFC operating on the CCM-DCM boundary [4–7] shapes the average input current by comparator/zero detector and is unconditionally stable. However, the natural simplicity, robustness, and stability of CrCM APFC are offset by high ripple current which cause increased conduction and core losses. Difficulties in filtering the variable frequency current ripple and poor efficiency restrict this technique to low-power and low-cost applications. Other Discontinuous Conduction Mode (DCM) based designs, which upside is simplicity suffer from similar problems exhibiting also higher harmonic distortion of the line current [8, 9].
APFC without line voltage sensing, [10–13] stands out as a robust, technologically simple, and cost-effective solution. A simple and clear physical insight into the principle of operation of the current loop of this class of APFCs was suggested in . All of the mentioned above APFCs with no input voltage sensing make use of a hidden current loop inside a DC-DC converter. The designs mainly differ in their method of realization of the transresistive feedback, PWM, and supplementary current loop control circuitry. Regardless of the implementation, however, the duty cycle programming is implemented according to the converters input port ideal average relationships and ideal modulator ramp signal. As a result, accurate current loop operation can only be attained in the Continuous Conduction Mode (CCM) under negligible current ripple conditions. In practice, however, the CCM-DCM mode changes, current ripple, and ramp carrier imperfections cause the duty cycle to deviate from the ideal relationship resulting in distortion in the average input current.
The very proper average current mode three-loop APFC [15–18] achieves its control objectives by a control scheme shown at Figure 1. The three-loop APFC uses a slow outer voltage loop to control the output voltage and a fast current loop for active shaping of the average input current. The reference signal for the inner current loop is derived from the rectified power line voltage by the multiplier-squarer-divider circuit. Additional outer feed-forward loop compensates for the line voltage variations. Such an APFC could be designed to operate in CCM most of the cycle but could tolerate also DCM intervals sustaining good current tracking.
The two feedback loops of the APFC of Figure 1 have conflicting objectives. In particular, a strong outer loop that manages to stabilize the output voltage will deteriorate the power factor by dictating an input current that ensures a fixed output voltage rather than the desired sinusoidal-shaped current. The outer loop is usually designed with a limited bandwidth as well as with a low gain so to heavily attenuate the output ripple. Otherwise, the ripple will distort the input current by penetrating into the reference of the current loop. As a result the response of the outer loop to load variations is rather slow. The outer loop error amplifier output voltage contains a second harmonic ripple component which modulates the current amplitude and thus distorts the current reference signal. Obviously, this also results in distorted line current.
This paper suggests that one of the causes of the major current distortion in most, if not all, APFC systems is the second harmonic ripple components that are brought into the current reference by the outer loops. The proposed solution to the problem can be found by compensating the output ripple rather than filtering. This alternative was investigated in this study analytically and by simulation. It was found that such a strategy is possible and furthermore it can easily be implemented by simple additional circuitry to commercially available APFC controllers. This paper presents the theory of the proposed approach and demonstrates the improvement in Total Harmonic Distortion (THD) that can be gained and provides design guidelines.
2. Basic Assumptions and Strategy
The analyses to follow are carried under the following assumptions:(a)the line voltage is a pure sinusoidal wave;(b)the rectifiers are ideal;(c)the power stage is linear and 100% efficient;(d)the current loop is ideal, that is, it forces the input current to follow the reference signal; (e)the holdup capacitor is large and hence the output ripple is small as compared to the dc output voltage.
The following approach is adopted: initially it is assumed that the input current is a pure sine wave. Next, the outer loop ripple components propagation mechanism into the current reference circuit is investigated. The assumption of the ideal current loop helps identify the current reference distortion components, which originate in the outer loops. Based on the results, the requirements for maintaining a distortion-free current reference are formulated. Finally, under the assumption of the ideal current loop, the residual distortion caused by the proposed ripple cancellation scheme is examined.
3. General Considerations: Review of APFC Output Current and Voltage
Under the assumptions above, the line voltage and current of the APFC of Figure 1 are in phase and of a sinusoidal shape. To simplify the notation the analyses are confined to one-half of the line period for which the rectified inputs can be expressed as where is the power line angle (). The instantaneous input power of the APFC is given by where is the average power over the power line cycle. The instantaneous charging power at the output of the APFC is a function of the output voltage, , and the output charging current, : Here, the output ripple is neglected, that is, the output voltage, , of the APFC is assumed to be equal to its average value, . For an ideal power stage with 100% efficiency, instantaneous input and output power are equal: Applying (2)–(4), the charging current, , is approximated to The holding capacitor current, , is the difference between the charging current and the DC load currents: The AC current of the holdup capacitor, , generates a second harmonics ripple component, , which appears at the output: Clearly, the output ripple is a linear function of power. The instantaneous output voltage including the second harmonic ripple can now be written as Using (7) yields The second harmonic frequency peak-to-peak ripple, , is derived from the above to be
4. The Feed-Forward Path Signal
The rectified input voltage fed to the feed-forward path filter (LPF) of the PFC topology under study, see Figure 1, can be represented by the Fourier series: where , , , and so forth are the Fourier coefficients. The relative phases of the harmonics are zero. When this signal is fed to the LPF feed-forward network of Figure 2, the LPF output voltage, , appears as where and are the gain and phase of the LPF transfer function at the th harmonic of the line frequency. Since the amplitude of the harmonics of the rectified voltage decreases with their frequency and since the LPF provides sufficient attenuation at high frequencies, harmonic components higher than the second one may be neglected at the output of the LPF. Therefore, the response of the LPF is approximated to The signal is squared with the gain of by the squarer circuit, see Figure 1. Applying the same reasoning as above the resulting quadratic term could be neglected. Therefore, the approximated feed-forward signal is Substituting the values of the Fourier coefficients, the expression for the feed-forward signal fed to the divider is obtained as where the term, and is the normalized feed-forward voltage: Equation (15) describes a waveform having a DC value proportional to the square of the amplitude of the input voltage, , scaled by the DC gain of the feed-forward path: . The normalized feed-forward signal (16) contains an undesirable second harmonic component propagating into the current reference. Interesting to note is that the normalized ripple (16) at the output of the LPF is constant and depends on the attenuation at the second harmonic frequency, . The amount of attenuation is determined by LPF configuration and its comer frequency. Lowering the corner frequency increases the attenuation, lowering also the harmonic contents of the feed-forward signal. This results in better line current quality. However, lowering the corner frequency slows the APFC response to line variations.
5. The Voltage Feedback Path Signal
To establish the operating point of the voltage error amplifier the issue of the input current generation should be addressed first. The input current of the PFC circuit of Figure 1 is generated by the following algorithm: where, is the voltage feedback error amplifier signal and is the system's gain constant. Thus the amplitude of the input current and the average input power are The advantage of the feed-forward path is apparent; the APFC power level (19) is independent of the line voltage.
The steady-state output voltage of the error amplifier, , contains the DC term, , as well as the second harmonics ripple component, : The steady state DC error amplifier voltage, , required to maintain the average power level, , could be derived from (19) neglecting the ripple component as The second harmonic component, , appears as the response of the error amplifier to the output voltage ripple, , given by (7) Here, the error amplifier's gain and phase, at the frequency of the second harmonic, are denoted and respectively. Combining (20), (21), and (22), yields the expression for the error amplifier output voltage delivered to the input of the divider as where is the normalized feedback voltage: Note that the normalized second harmonic ripple component at the output of the error amplifier is constant and independent of the power level output voltage of the APFC. This observation forms the basis for the following development of the proposed ripple cancellation method.
6. The Current Programming Signal
To produce the correct current programming signal, the APFC circuit of Figure 1 uses the divider output, , to modulate the line voltage waveform. The divider output signal is calculated using (15) and (23) yielding Here, is the divider gain constant and is the normalized divider output: The current programming signal, , produced by modulation of the line voltage (1) with the divider output (25) is given by where is the multiplier gain constant. The current programming signal amplitude is therefore Equations (27) and (28) reveal the mechanism by which distortion components of the outer loops are introduced into the current reference. The term contains harmonic components which modulates the current programming signal amplitude (28). Consequently, the input current of the APFC could not possibly be any less distorted than (27).
7. The Power Gain Constant
When the current loop tightly regulates the input current, the output voltage of the current sensing network, , see Figure 1, is forced to follow the current programming signal, : In the most common case, the current sensing network is just a series resistance, , so the amplitude of the sensed voltage is The power gain constant may be found substituting (28), (30) into (29) and assuming an ideal , that is, (26) equals unity. This gives This relationship remains valid also for the general case, when the current sensing network transfer function low frequency gain is denoted by .
8. Filter Design for Minimum Line Current Distortion
Examination of (27) and (28) reveals that any harmonic disturbances at the divider output will produce cross products with the sine term. This will appear as harmonics in the current programming signal and cause distortion in the input current. Traditionally, the designers [15–18] minimize the distortion by providing large attenuation of the second harmonic, that is, minimizing the and terms in (16), (24), and (26). However, this has only a limited success for the following reasons. To ensure stability and adequate phase margin, the error amplifier usually has a single-pole transfer function of −20 db/decade gain roll off beyond its corner frequency and its filtering action is poor. Since the ripple frequency is quite low the bandwidth of the error amplifier is severely restricted resulting in poor transient response. A high-order low-pass filter may be used to achieve efficient filtering of the average component of the rectified input voltage. However, once again due to the low second harmonic frequency the filter has a narrow bandwidth and its transient response is rather poor. Here an alternative approach is proposed. Equations (27) and (28) suggest that it is possible to achieve distortion-free current programming signal by making the normalized divider output (26) equal unity: To satisfy (32) requires that the normalized ripple components of the error and the feed-forward signals be equal both in amplitude and phase: Since the normalized ripple components are of the same frequency and of a constant amplitude, it is possible to fulfill (34) by proper controller circuit design. For this purpose both amplitude and phase conditions must be satisfied. The amplitude condition defines the LPF attenuation needed to equate the amplitudes of the ripple components: This could be rearranged using (31) into the following form: where, is the line frequency.
The phase condition could be derived by equating the sine and cosine terms in (33) and using elementary trigonometry relationship: Thus, the required phase shift of the LPF at the second harmonic frequency is The error amplifier transfer function is determined primarily by the stability and performance considerations of the outer loop. Consequently, to make the solutions of (34), (37) unique, the design of the feed-forward filter should be carried out after the complete knowledge of the error amplifier characteristics is gained. Note that , as defined by (22), is the overall error amplifier phase shift. Since the phase shift of a single-pole error amplifier lags from the initial +180 degrees, due to the inverting configuration, to about +90, applying (37) requires about 0/360 degrees of LPF phase shift. Designing the feed-forward path filter according to the amplitude and phase conditions stated above will ensure minimum distortion of the PFC input current. It should be emphasized that, under the assumptions made, this approach will render a perfect current programming signal independent of the APFC power level.
9. Simulation Results
To study the performance of the APFC circuit of Figure 1, the system's model was simulated by PSPICE circuit simulator. The simulation was focused on the performance of the feedback and feed-forward loops under the assumption that the inner loop is ideal. The inner loop and power stage models were characterized by (4), (5), and (16) and implemented in PSPICE according to these behavioral relationships, see Figure 2. The design of the feed-forward LPF and voltage feedback amplifier followed the procedure discussed in [15, 16]. The program simulated a closed-loop PFC system fed by a rectified 110 V/60 Hz line and delivers at to a resistive load of . The holdup capacitor of 450 uF was chosen. The overall squarer-multiplier-divider constant, defined by external resistors, was set to . Current sense resistor used was . According to Figure 3(b), the feed-forward filter transfer function was: . For these conditions, the numerical value of expression (31) equals .
To demonstrate the validity of the proposed ripple cancellation method, the LPF of the feed-forward network was modified to follow (34) and (37) as shown at Figure 3(b). New values were given to the error amplifier parameters as depicted in Figure 3(c). The simulation results of the original and proposed circuits are presented in Figures 4(a) and 4(b). Here, the normalized outputs of the voltage error amplifier, feed-forward, and divider circuits are shown. Comparison of the results reveals that the amplitude of the ripple voltage at the divider output is greatly reduced by the proposed method, reducing also the THD of the simulated APFC system. The normalized rectified line voltage and current as well as the APFC's charging currents are shown in Figure 4(c). Fourier analysis was carried out by SPICE on the simulated line current. Fourier analysis results are given in Tables 1, 2 and 3. The analysis reveals that the distorted current programming signal of the original design, see Table 1, contributes 1.86% to the total harmonic distortion of the APFC system, which is rather good performance index, whereas, using the proposed method the distortion is reduced to a negligible level of only 0.19%, see Table 2. That is about one order of magnitude improvement of THD.
One of the main sources of input current distortion in high-frequency APFC systems is the output voltage ripple which propagates into the feedback loop as well as the second harmonic of the line voltage injected through the feed-forward loop. These signals adversely affect the current reference signal quality.
This paper examined the propagation of the ripple components in the feedback and feed-forward loops of the APFC controller circuits and their interaction within the current shaping network. Based on this analysis, a ripple cancellation method is proposed. Analytical results are confirmed by simulation and show good agreement with predicted theoretical results. The simulation results suggest that the proposed method can reduce the THD of the input current of PFC system by more than an order of magnitude. The present analysis and simulation were carried out under some simplifying assumptions, yet, second-order effects proved to be negligible.
Another important advantage of the proposed method is a dramatic increase of the error amplifier bandwidth, see Figure 5. This is possible in view of the fact that effective ripple cancellation requires a lesser amount of error amplifier attenuation of the second-line harmonic. Therefore, the outer feedback loop bandwidth becomes dominated by the relatively large holding capacitor, which value is determined primarily by the energy storage requirements.
The discussion of this paper is confined to the topology of one family of APFC controllers (Figure 1); however, the proposed approach could be expanded to other APFC schemes by following the idea of ripple compensation developed here.
- K. N. Sakthivel, S. K. Das, and K. R. Kini, “Importance of quality AC power distribution and understanding of EMC standards IEC, 61000-3-2, IEC, 61000-3-3 & IEC, 61000-3-11,” in Proceedings of the 8th International Conference on Electromagnetic Interference and Compatibility, pp. 423–430, 2003.
- B. Singh, B. N. Singh, A. Chandra, K. Al-Haddad, A. Pandey, and D. P. Kothari, “A review of single-phase improved power quality AC-DC converters,” IEEE Transactions on Industrial Electronics, vol. 50, no. 5, pp. 962–981, 2003.
- M. M. Jovanović and Y. Jang, “State-of-the-art, single-phase, active power-factor-correction techniques for high-power applications—an overview,” IEEE Transactions on Industrial Electronics, vol. 52, no. 3, pp. 701–708, 2005.
- B. Andreycak, “Power factor correction using UC3852 controlled on-time zero current switching technique,” U-132 Application note, Unitrode Integrated Circuits.
- M. Marvi and A. Fotowat-Ahmady, “A fully ZVS critical conduction mode boost PFC,” IEEE Transactions on Power Electronics, vol. 27, no. 4, pp. 1958–1965, 2012.
- T. F. Wu, J. R. Tsai, Y. M. Chen, and Z. H. Tsai, “Integrated circuits of a PFC controller for interleaved critical-mode boost converters,” in Proceedings of the 22nd Annual IEEE Applied Power Electronics Conference and Exposition (APEC '07), pp. 1347–1350, March 2007.
- J. R. Tsai, T. F. Wu, C. Y. Wu, Y. M. Chen, and M. C. Lee, “Interleaving phase shifters for critical-mode boost PFC,” IEEE Transactions on Power Electronics, vol. 23, no. 3, pp. 1348–1357, 2008.
- K. De Gussemé, D. M. Van de Sype, A. P. M. Van den Bossche, and J. A. Melkebeek, “Input-current distortion of CCM boost PFC converters operated in DCM,” IEEE Transactions on Industrial Electronics, vol. 54, no. 2, pp. 858–865, 2007.
- K. H. Liu and Y. L. Lin, “Current waveform distortion in power factor correction circuits employing discontinuous-mode boost converters,” in Proceedings of the 20th Annual IEEE Power Electronics Specialists Conference (PESC '89), pp. 825–829, June 1989.
- D. Maksimović, Y. Jang, and R. W. Erickson, “Nonlinear-carrier control for high-power-factor boost rectifiers,” IEEE Transactions on Power Electronics, vol. 11, no. 4, pp. 578–584, 1996.
- J. P. Gegner and C. Q. Lee, “Linear peak current mode control: a simple active power factor correction control technique for continuous conduction mode,” in Proceedings of the 27th Annual IEEE Power Electronics Specialists Conference (PESC '96), pp. 196–202, January 1996.
- Z. Lai and K. M. Smedley, “Family of power-factor-correction controllers,” in Proceedings of the IEEE 12th Applied Power Electronics Conference (APEC '97), pp. 66–73, February 1997.
- J. Rajagopalan, F. C. Lee, and P. Nora, “Generalized technique for derivation of average current mode control laws for power factor correction without input voltage sensing,” in Proceedings of the IEEE 12th Applied Power Electronics Conference, pp. 81–87, February 1997.
- S. Ben-Yaakov and I. Zeltser, “The dynamics of a PWM boost converter with resistive input,” IEEE Transactions on Industrial Electronics, vol. 46, no. 3, pp. 613–619, 1999.
- P. C. Todd, “UC3854 controlled power factor correction circuit design,” U-134 Application note, Unitrode Integrated Circuits.
- J. B. Williams, “Design of feedback loop in unity power factor AC to DC converter,” in Proceedings of the 20th Annual IEEE Power Electronics Specialists Conference (PESC '89), pp. 959–967, June 1989.
- L. H. Dixon, “High power factor preregulators for offline power supplies,” in Proceedings of the Unitrode Seminar, 1993.
- L. H. Dixon, “High power factor preregulator design optimization,” in Proceedings of the Unitrode Seminar, 1992.