- About this Journal ·
- Abstracting and Indexing ·
- Aims and Scope ·
- Article Processing Charges ·
- Articles in Press ·
- Author Guidelines ·
- Bibliographic Information ·
- Citations to this Journal ·
- Contact Information ·
- Editorial Board ·
- Editorial Workflow ·
- Free eTOC Alerts ·
- Publication Ethics ·
- Reviewers Acknowledgment ·
- Submit a Manuscript ·
- Subscription Information ·
- Table of Contents
Advances in Power Electronics
Volume 2012 (2012), Article ID 409671, 10 pages
FPGA-Based Fixed Point Implementation of a Real-Time Induction Motor Emulator
L.S.E., Ecole Nationale d'Ingénieur de Tunis, BP 37, 1002 Le Belvédère, Tunisia
Received 18 May 2012; Revised 12 September 2012; Accepted 18 September 2012
Academic Editor: Jose Pomilio
Copyright © 2012 L. Charaabi. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.
This paper investigates the numerical issue of a discrete-time induction-motor emulator implementation. The stability analysis of the finite-word-length implementation shows a coupling between required word length and the sample rate. We propose specific guidelines to analyze this coupling and to estimate the required data word length for both signals and coefficients of the model. To respect algorithm requirements, an FPGA-based implementation was used for architecture development. The direct torque control is implemented to verify in real time the AC-motor emulator prototype.
Control algorithms of electrical drives are usually tested by the attachment of electrical motors. Experimental testing requires direct measuring by employing measurement instrumentation and sensors that would be complex, impractical, noise sensitive, and expensive. Traditionally these tests are performed on motor and inverter models under software simulation environments which are, in most cases, non-real-time and unable to exactly replicate real operational conditions.
In order to provide a real-time verification of the implemented control algorithm and increase the realism of simulation, the control algorithm is tested while connected to a real-time emulator for the plant (induction motor and inverter) . Due to their high capacities of executing in real-time complex algorithm, FPGA technology is a good candidate for this kind of RT emulator .
For reasons of cost, simplicity, speeds and memory space, the real-time emulator of the induction motor is performed with the Euler’s shift discretization method and quantized with fixed point format .
The robustness of the discretized algorithm is a critical issue in fixed-point format implementation. It is well known that, stable, closed-loop system may become unstable when the algorithm is implemented using a fixed-point processor due to finite-word-length effects. The fractional part precisions in fixed point are chosen to guarantee a minimum signal-to-noise ratio for finite-word-length quantization effects. The integer part is computed using norms .
In an FPGA implementation, it is possible to use separate fixed-point format for each coefficient and signal in the algorithm. Hence, the use of FPGA allows maintaining a higher computational precision at critical points.
In this paper, authors propose a real-time induction motor emulator designed in fixed point format for an FPGA implementation. The starting point is a continuous-time model. Discrete-time models are derived using the traditional shift form approximation. A study in terms of stability and finite-world-length effects is shown and a design technique for choosing the coefficient and signal bit widths is given [5, 6].
To demonstrate the accurateness of the real-time induction motor emulator, a particular example is developed: the direct torque control (DTC) of an induction motor .
The paper is organized as follows. The second section reminds the algorithmic study of a discrete-time induction motor model-based shift form approximation. Section 3 gives an efficient methodology for choosing the finite fixed-point word length. Section 4 shows the FPGA-based architecture development and gives emulation results of the induction motor emulator with the DTC algorithm.
2. Discrete-Time Model Based on Shift Form Approximation
The block diagram of the complete system is outlined in Figure 1 including the control scheme, the induction motor, and the power chain.
As it can be seen, the DTC algorithm is decomposed in three specific blocks.(i)Transformation block, which is composed by two subalgorithms based on the direct Concordia transformation algorithm for the current and voltage three phases models.(ii)Estimation block, which is composed by the calculation subalgorithms of flux , torque (), and flux sector position. The discrete-time model of the flux subalgorithm is based on the shift form approximation: (iii)command block, which is composed by a look-up table (LUT) corresponding to the switching function of the power inverter.
In order to provide a real-time verification of the implemented control algorithm, the DTC is tested while connected to a real-time emulator for the induction motor and inverter.
The induction machine is a nonlinear high-order system and for this reason complicated models must be used to control it. The dynamic behaviour of the induction motors can be described by a set of differential equations in a rotating reference frame with an angular velocity of . Moreover it is assumed that a stationary reference frame is fixed to the stator axis. The proposed model also assumes the classical decoupling between mechanical and electrical modes. It yields that under these assumptions, the state model of the induction motor (IM) is  where, matrices , , , and are 4-by-4, 4-by-2, 4-by-4, and 4-by-2, respectively:
is the rotor time constant, is leakage coefficient with , and is the angular velocity.
The purpose of this section is to develop a computationally efficient discrete-time approximation of the continuous motor model operating in real time.
The most used discretization method is based on Forward shift approximation . The shift form approximation is given by where is the sampling period.
Introducing (5) in yields where
The data flow graph (DFG) corresponding to the induction motor model is presented in Figure 2. Coefficients depend on the parameters of the machine and are obtained for a per unit model.
The following lines show the different coefficients used for the per unit (PU) DTC algorithm where, , , , , and .
The base values are determined from the maximal values by using the following equations, where , , and are, respectively, the phase maximal current, the phase to neutral maximal voltage, and the maximal frequency of the induction motor:
And if we consider the solution at the instant , we obtain
Therefore, the matrices that rule the continuous and discrete time systems are, respectively, and , and, consequently, the continuous and discrete time systems will be described by the eigenvalues or the poles of these matrices.
The poles of the matrix are , being a pole of the matrix of the continuous time system; the poles of the matrix are .
In this study, a low power induction motor (1.5 kW) has been considered. The corresponding continuous-time model has four poles for electromagnetic model as illustrated below:
Let us suppose the following quadratic error function:
Therefore, for sampling periods tending to zero the difference between and becomes very small for each pole of , and, consequently, it will optimize the resemblance between the time-domain response of the continuous-time and the discrete-time system.
Discrete-time systems resulting from the shift form approximation are sometime unstable. It is possible, however, to select the sampling rate such that the discrete-time system is always stable when the corresponding continuous-time system is stable. For the shift form realization, the stability domain is located inside the unit circle. Therefore, a -domain pole is stable if its module is less than one:
Therefore, the most critical -domain pole corresponds to the -domain pole having the greatest module. The pole has the greatest module as function of .
The locations of poles of the motor for different sampling rate values are shown in Figure 3. It can be seen that for high sampling rate, the poles become very close to one. This can be problematic, particularly when finite precision formats are considered.
3. Efficient Methodology for Choosing the Word Length of Coefficients and Variables
The following methodology is developed for choosing each coefficient and variable bit width.
3.1. Representation of Coefficients
When the model is implemented in fixed-point format, each coefficient must be given a finite-precision representation composed by an integer and fractional part. Each part is estimated separately.
The integer part position for a coefficient must be estimated by taking the base 2 logarithm of the maximum coefficient: where rounds to the nearest integer less than or equal to .
The fractional part must be determined by the maximum allowable perturbation of the coefficient from its ideal infinite-precision value. This can be achieved by computing the quantized parameter deviation or sensitivity and the stability margin. The angular velocity is selected to be the worst-case value. By means of Figure 3, for pole and its conjugate, is fixed to the maximal value and for pole and its conjugate is equal to zero.
Let be the quantized parameter set consisting of all quantized coefficients of the state matrix . When the model is implemented in fixed-point format, each coefficient of the set is perturbed:
Due to the finite-word-length effects, each perturbation is bounded by where is the number of bits of the fractional part.
Due to the perturbation each pole is moved to and it follows from a first-order approximation that the deviation can be computed with where is the number of modified parameters .
As an example, for poles and , the worst-case deviation is obtained with . Then, the expression of deviation with, and .
The quantized pole may be outside the unit circle, especially with high sampling rate; thus, it is critical to know when the finite-word-length error leads to instability. This means to determine how close are to the unit circle. Let us consider the following related measure for each pole: where is called the stability margin of the th pole and is a prescribed maximum allowable percent change in pole location relative to the stability margin.
Assuming that all coefficients have the same word-length fractional part, then ; it follows from inequality (21) that
For the studied motor, setting and s, the conditions (23) yield 19 bits for fractional part word length for matrix coefficients.
3.2. Representation of Signals
The next step in the fixed-point motor model implementation is to estimate the format for each signal. An incremental methodology is used to determine the appropriate representation for the state variables. As shown in Figure 4, the first step is to find transfer function from each input and the appropriate signal in the DFG. Then the dynamic range (maximum amplitude) of each signal is carried out by using and norms, and, thus, the integer word length range is identified. Finally, the fractional part word-length is estimated by analysis of the signal-to-quantization-noise ratio (SQNR) for each signal.
The dynamic range (maximum amplitude) of each signal of the DFG allows identifying their integer range. In practice the maximal current supported by the motor as well as the maximal produced torque and fluxes is known. Therefore, for the per-unit motor model, these dynamic ranges are bounded by 1. Notice that the voltage inputs and the electrical velocity are also normalized. Thus, these dynamic ranges are all bounded by 1: where denotes the the norm, defined by
Now considering internal signals of the DFG, one can see that
Therefore, signals and are bounded by the same quantity:
The integer part word length of all the signals is then estimated by taking the base 2 logarithm of the range bound. Table 1 illustrates the signal range bounds and the corresponding integer part word length.
The fractional part word length is estimated by analyzing the signal-to-quantization-noise ratio (SQNR) for each signal . The SQNR is measured in decibels as
There are two possible sources of quantization noise in the induction motor emulator implementation, namely:(i)the noise introduced by the limited resolution of a possible control technique, producing an input noise variance ,(ii)the truncation noise which is introduced when products or sums are quantized. This noise propagates through the emulator and appears at outputs.
It is assumed that the quantization noise has the following properties.(i)Each quantization noise source is a stationary white noise process.(ii)Each noise source is uncorrelated with all other noise sources and the input of the system.(iii)The error resulting from quantization can then be modeled as a random variable uniformly distributed over the appropriate error range. Therefore, the noise variance due to truncation is where is the fractional part word length.
To investigate the noise propagation, a noise quantization model of the induction motor emulator is developed in Figure 5. The addition is performed without truncation. The quantization is performed after each multiplication; the quantization noise resulting from multiplications is therefore -times higher than the one generated by a single multiplication. It yields that the variances of noise and are
The output noise variances can be estimated using the matrix transfer function from the input vector to the output vector . Using matrix notation in (5), the transfer function matrix response is where
Let denote the impulse response from input to output for a linear system. Assuming that the input signal has a maximal value , the output must be bounded  so that where denotes the norm, defined by .
Each coefficient is computed to have a maximal value as function of electrical velocity :
The norms of discrete-time impulse responses corresponding to these transfer functions are computed approximately by finite sums. Figure 6 shows the impulse response for each coefficient of the matrix .
Assuming that all signals have the same word length, the first inequality gives the worst-case variance error and therefore the fractional part word length will be selected taking into account this condition.
The variances of the sinusoidal input and output signals of the induction motor emulator are expressed in terms of the root mean square. Hence (18) gives
Assume that where is the fractional part word length of the input voltage. The resolution is strongly dependent on the PWM one.
Figure 7 shows the SQNR as function of the fractional part word length for different bits. With a 10-bit word-length, we obtain for 18-bit wordlength.
4. FPGA-Based Induction Motor Emulator
4.1. System Architecture
The induction motor emulator is implemented using modular and standard design principles on a Xilinx Development kit, which contain a FPGA from SPARTAN III family, the XC3s200.
The emulator module requires important hardware resource. Therefore, the corresponding architecture is optimized in terms of consumed resources by the AAA methodology  which leads to only 3 multipliers.
As in , the proposed architecture consists in a control unit and a data path. The control unit generates a suitable timing schedule to control the data path and other local sequencers. Figure 8 depicts the proposed system architecture.
After the specification of the algorithm with data wordlength and sampling frequency, we propose to develop a modular architecture for the induction motor model to be implemented through an FPGA device.
4.2. System Architecture under Test in Open Loop
Figure 9 depicts the proposed system architecture. It includes a set of dedicated modules to guarantee the real-time hardware in the loop (HIL) simulation.
The functional blocks of the global architecture are listed below.(i)The UART (Universal Asynchronous Receiver Transmitter) module that provides a serial communication between the host PC and the implemented architecture. The UART allows both reconfigurations in real time of the induction motor model by tuning its coefficients and data acquisition to be visualized on the PC. To solve the dialogs between the UART implemented on the FPGA board and the PC, MATLAB's serial port interface is used.(ii)The input voltage stimuli module. It generates three digital values, which represent the three phases voltage. One can control the output waves amplitude and frequency in real time via the UART module. This module is used to test the induction motor (IM) module.(iii)The IM module that requires the most important hardware resources. It implements the induction motor model.(iv)The global sequencer module. It represents the control unit that generates a suitable timing schedule to control data path and other local sequencers.
The real-time simulation results presented in Figure 10 with 10 kHz sampling frequency show a slight difference between the torque produced by the implemented motor model architecture and the simulated torque under MATLAB environment under continuous-time conditions. This difference is too small to affect the performance of the real-time model.
4.3. System Architecture under Test with DTC Algorithm
The DTC is a well-known induction motor control strategy . This control algorithm is selected to be tested with the real time induction motor model. The implemented architecture of the DTC control algorithm has been tested with the induction motor model architecture in real time. Figure 11 illustrates the proposed real time test bed. It includes a set of dedicated modules to guarantee a real-time simulation.(i)The UART (Universal Asynchronous Receiver Transmitter) module that provides a serial communication between the host PC and the implemented architecture. (ii)The stimuli module. It generates the references for the DTC control algorithm.
The torque and the stator flux are collected from the serial interface and visualized under Matlab-Simulink environment. Figure 12 illustrates the real-time emulation results.
This work has presented an optimized fixed-point format induction motor model intended for real-time simulation and emulation. With the analysis of the coupling between the sample rate and the data word length, this work has provided a theoretical guideline to find the optimal hardware implementation. The proposed architecture of the model has been successfully verified by the development and implementation of a real-time test bed that contains the AC-motor model and a DTC control algorithm.
The methodology for estimating the appropriate data word length may be applied to other various discrete-time system realizations.
This paper was supported by the Tunisian Ministry of High Education and Research: UR-LSE-ENIT-03/UR/ES05.
- S. Lentijo, A. Monti, E. Santi, C. Welch, and R. Dougal, “A new testing tool for power electronic digital control,” in Proceedings of the IEEE 34th Annual Power Electronics Specialists Conference, vol. 1, pp. 81–87, Acapulco, Mexico, June 2003.
- T. Grandpierre, C. Lavarenne, and Y. Sorel, “Optimized rapid prototyping for real-time embedded heterogeneous multiprocessors,” in Proceedings of the 1999 7th International Conference on Hardware/Software Codesign (CODES '99), pp. 74–78, Rome, Italy, May 1999.
- J. Wu, S. Chen, G. Li, and J. Chu, “Optimal finite-precision state-estimate feedback controller realizations of discrete-time systems,” IEEE Transactions on Automatic Control, vol. 45, no. 8, pp. 1550–1554, 2000.
- D. Menard and O. Sentieys, “Automatic evaluation of the accuracy of fixed-point algorithms,” in Proceedings of the IEEE/ACM Conference on Design, Automation and Test in Europe (DATE '02), Paris, France, March 2002.
- H.-M. Cheng and G. T.-C. Chiu, “Coupling between sample rate and required wordlength for finite precision controller implementation with delta transform,” in Proceedings of the American Control Conference (ACC '07), pp. 3588–3593, New York, NY, USA, July 2007.
- R. S. H. Istepanian, G. Li, J. Wu, and J. Chu, “Analysis of sensitivity measures of finite-precision digital controller structures with closed-loop stability bounds,” IEEE Proceedings of control Theory Application, vol. 145, no. 5, pp. 472–478, 1998.
- I. Takahachi and T. Nogushi, “A new quick response and high efficiency control strategy of an induction motor,” IEEE Transactions on Industry Applications, vol. IA-22, no. 5, pp. 820–827, 1986.
- O. Vainio, S. J. Ovaska, and J. J. Pasanen, “A digital signal processing approach to real-time AC motor modeling,” IEEE Transactions on Industrial Electronics, vol. 39, no. 1, pp. 36–45, 1992.
- L. Charaabi, E. Monmasson, and I. Slama-Belkhodja, “FPGA-based real-time emulation of induction motor using fixed point representation,” in Proceedings of the 34th Annual Conference of the IEEE Industrial Electronics Society (IECON '08), pp. 2393–2398, November 2008.
- Z. Fang, J. E. Carletta, and R. J. Veillette, “A methodology for FPGA-based control implementation,” IEEE Transactions on Control Systems Technology, vol. 13, no. 6, pp. 977–987, 2005.
- M. H. Hayes, Schaum's Outline of Theory and Problems of Digital Signal Processing, McGraw-Hill, New York, NY, USA, 1998.
- T. Grandpierre, C. Lavarenne, and Y. Sorel, “Optimized rapid prototyping for real-time embedded heterogeneous multiprocessors,” in Proceedings of the 1999 7th International Conference on Hardware/Software Codesign (CODES'99), pp. 74–78, May 1999.
- E. Monmasson and M. N. Cirstea, “FPGA design methodology for industrial control systems-a review,” IEEE Transactions on Industrial Electronics, vol. 54, no. 4, pp. 1824–1842, 2007.