Comparison of Duty Cycle Generator Algorithms for SPICE Simulation of SMPS

Figure 5

PSPICE simulation diagram of the Average Current mode APFC current loop (a); Simulation of the current loop frequency responses (b); time domain waveforms of the scaled line voltage Vline/100 and line current 𝐼(Vline) (top), and the duty cycles Don, Doff; note that the sum 𝐷_off+𝐷_off<1 as DCM commences (bottom) (c).

(a)

(b)

(c)