Modeling of Transistor's Tracking Behavior in Compact Models

Abstract

We present a novel method to model the tracking behavior of semiconductor transistors undergoing across-chip variations in a compact Monte Carlo model for SPICE simulations and show an enablement of simultaneous 𝑁(𝑁−1)/2 tracking relations among 𝑁 transistors on a chip at any poly density, any gate pitch, and any physical location for the first time. At smaller separations, our modeled tracking relation versus physical location reduces to Pelgrom's characterization on device's distance-dependent mismatch. Our method is very compact, since we do not use a matrix or a set of eigen solutions to represent correlations among 𝑁 transistors.

1. Introduction

As semiconductor feature size decreases, the statistical variations in circuit’s characteristic, caused by statistical variations in semiconductor processes, become increasingly severe. There have been many studies on the characterization, simulation, and modeling of such statistical variations, especially on interdie and intradie/across-chip variations and device tracking behavior in recent years [1–9]. In a statistical description of a process, device, or circuit’s variability, one important aspect is the modeling of across-chip variations (ACV) or device tracking in a SPICE model. In this paper, we present a novel method to model the tracking behavior of semiconductor transistors undergoing across-chip variations in a compact Monte Carlo model for SPICE simulations, and show an enablement of simultaneous 𝑁(𝑁−1)/2 tracking relations among 𝑁 transistors on a chip at any poly density, any gate pitch, and any physical location for the first time. At smaller separations, our modeled tracking relation versus physical location reduces to Pelgrom’s characterization on device’s distance-dependent mismatch. Our method is very compact, since we do not use a matrix or a set of eigen solutions to represent correlations among 𝑁 transistors.

2. Modeling of FET’s Tracking Behavior

2.1. Modeling the Effect of Polysilicon Density on FET Channel Length’s Tracking

Field effect transistor (FET) channel length’s tracking relations are impacted by differences in poly pattern density. Poly pattern density is defined as the percent of total poly area within a given area (say, an area of 200 μm × 200 μm), which is a relatively small area from a wafer polish viewpoint but is very large compared to the size of a transistor. For all poly densities (within an allowed range; say, between 𝑧_min=20% and 𝑧_max=80%), the standard deviation of a single transistor’s channel length is a constant (covering all lots), independent of the poly pattern density 𝑧 around it. However, the tracking in channel length between two FETs is impacted by the difference between two poly density values around each of them. When two FETs have similar poly density values, their channel lengths are more likely to be the same on a given chip. On the other hand, when two FETs have different poly densities around each of them, their channel lengths are more likely to be different on a given chip. Quantitatively, a characterization goes like the following. For a group of 𝑁(≥2) FETs in a small area with a same gate pitch but different poly densities, (a) all FETs have the same nominal channel length 𝐿₀, independent of poly density 𝑧 around each FET,𝐿_𝑖𝑧_𝑖=𝐿₀,𝑖=1,2,3,…,𝑁, (1) where 𝑧_𝑖 is the poly density around the 𝑖th FET; (b) all FETs have the same variance for channel length, independent of poly density 𝑧 around each FET,𝐿_𝑖𝑧_𝑖−𝐿_𝑖𝑧_𝑖²=𝜎²_uc+𝜎²_𝑑+𝜎²_cm,𝑖=1,2,3,…,𝑁, (2) where 𝜎_uc is completely uncorrelated part of channel length variations, 𝜎_cm is chip-mean (completely correlated) part of variations, and 𝜎_𝑑 represents a partially correlated ACLV component that is associated with poly density’s change on a chip; (c) the tracking between the channel length 𝐿_𝑖 of the 𝑖th FET and the channel length 𝐿_𝑗 of the 𝑗th FET, however, is a function of the difference between the poly density 𝑧_𝑖 around the 𝑖th FET and the poly density 𝑧_𝑗 around the 𝑗th FET, 𝐿_𝑖𝑧_𝑖−𝐿_𝑗𝑧_𝑗²=𝑓₁𝑧_𝑖−𝑧_𝑗,𝑖,𝑗=1,2,3,…,𝑁,𝑖≠𝑗, (3) with two limiting values,𝐿_𝑖𝑧_𝑖−𝐿_𝑗𝑧_𝑗²⟶2𝜎²_ucif𝑧_𝑖⟶𝑧_𝑗,2𝜎²_uc+𝜎²_𝑑if𝑧_𝑖⟶𝑧_min,𝑧_𝑗⟶𝑧_max. (4) Notice that (3) gives 𝑁(𝑁−1)/2 tracking relations among 𝑁 FETs. In (3) and (4), poly densities are bounded at both ends,𝑧_min≤𝑧_𝑖,𝑧_𝑗≤𝑧_max,𝑖,𝑗=1,2,3,…,𝑁,𝑖≠𝑗. (5) Also in (3), 𝑓₁(▵𝑧) is a continuous and symmetric function of ▵𝑧 and increases monotonically with |▵𝑧|. It is very important to characterize both single-device’s tolerance and the tracking/mismatch between two devices separately. It is a challenge to find a stochastic function which leads to tracking behavior (3) for three or more FETs (𝑁≥3) simultaneously. A difficulty lies in this: how to net list the 𝑖th FET without entering all other FETs information into the model call for the 𝑖th FET? There are only a few solutions.

We use polysilicon density 𝑧 as a model instance parameter in an FET’s compact model. The Monte Carlo model for improved ACLV modeling is𝐿_𝑖=𝐿₀+𝐺₀𝜎_cm+𝑔_𝑖𝜎_uc+𝐺₁𝜎_𝑑𝜋𝑧cos^𝑖−𝑧_min2𝑧_max−𝑧_min+𝐺₂𝜎_𝑑𝜋𝑧sin^𝑖−𝑧_min2𝑧_max−𝑧_min,𝑖=1,2,3,…,𝑁. (6) In (6) and in the rest of the paper, each of 𝐺₀,𝐺₁,𝐺₂,𝐺₃,…,𝑔₁,𝑔₂,𝑔₃,… is an independent stochastic variable of mean zero and standard deviation one. For a pre-layout (i.e., schematic) FET model in which poly density is not known at net list time, 𝑧_𝑖 can be a random value between 𝑧_min and 𝑧_max. Using Monte Carlo model (6), it is easy to see that requirement (1) is satisfied and so is requirement (2). Also using model (6), 𝑁(𝑁−1)/2 tracking relations among 𝑁 FET’s channel lengths are found to be 𝐿_𝑖−𝐿_𝑗²=2𝜎²_uc+4𝜎²_𝑑sin²𝜋𝑧_𝑖−𝑧_𝑗4𝑧_max−𝑧_min,𝑖,𝑗=1,2,3,…,𝑁, (7) which depends on the poly density difference |𝑧_𝑖−𝑧_𝑗| only. Comparing (7) with (3), one gets an explicit expression of the function 𝑓₁(𝑧_𝑖−𝑧_𝑗). We want to point out that there is no matrix, no eigenvalues, and no eigenvectors in Monte Carlo model (6). The Monte Carlo model (6) applies to other device/circuit tracking/ACV problems in which tracking between any two devices/circuits among a group of devices/circuits is a function of the difference of two parameter values associated with the two devices/circuits.

2.2. Modeling the Effect of Gate Pitch on FET Channel Length’s Tracking

In a given semiconductor technology, there is a minimum gate pitch (𝑝_min), which is related to the lithography print capability used for the semiconductor technology. Note that a gate pitch is the sum of poly width (i.e., FET channel’s design length) and poly-to-poly space. At the minimum gate pitch, poly width is typically at the minimum poly width for the given semiconductor technology. Besides a minimum gate pitch (𝑝_min), other larger gate pitch values (say, twice of 𝑝_min, four times of 𝑝_min, etc.) are also allowed. At a given larger gate pitch, poly width can take several different values. In other words, even at a single transistor’s layout level, there may not be any relation between a gate pitch and a local poly density. Since poly pattern density is an averaged value over a large area of, say, 200 μm × 200 μm, gate pitch and poly density are treated as two independent quantities. Often, a semiconductor company characterizes the effect of gate pitch and the effect of poly density separately. A characterization of the single channel length’s tolerance and the tracking between two channel lengths goes like the following. For a group of 𝑁 CMOS FETs within a small area (say, within an area of 200 μm × 200 μm), there is a fixed value 𝑧 for poly pattern density, but these 𝑁 CMOS FETs can have different gate pitches. Quantitatively, (a) all FETs have the same nominal channel length 𝐿₀, independent of gate pitch 𝑝,𝐿_𝑖𝑝_𝑖=𝐿₀,𝑝_𝑖≥𝑝_min,𝑖=1,2,3,…,𝑁, (8) where 𝑝_𝑖 is the gate pitch of the 𝑖th FET. (b) All FETs have the same variance for channel length, independent of gate pitch 𝑝,𝐿_𝑖𝑝_𝑖−𝐿₀²=𝜎²_uc+𝜎²_𝑝+𝜎²_cm,𝑝_𝑖≥𝑝_min,𝑖=1,2,3,…,𝑁, (9) where𝜎_𝑝is a component of ACLV variation that is associated with gate pitch variations on a chip. And (c) the tracking between the channel length 𝐿_𝑖 of the 𝑖th FET and the channel length 𝐿_𝑗 of the 𝑗th FET, however, is a function of the ratio between the gate pitch 𝑝_𝑖 of the 𝑖th FET and the gate pitch 𝑝_𝑗 of the 𝑗th FET, 𝐿_𝑖𝑝_𝑖−𝐿_𝑗𝑝_𝑗²=𝑓₂𝑝_𝑖𝑝_𝑗,𝑝_min≤𝑝_𝑖,𝑝_𝑗≤𝑝_upper,𝑖,𝑗=1,2,3,…,𝑁,𝑖≠𝑗, (10) with two limiting values,𝐿_𝑖𝑝_𝑖−𝐿_𝑗𝑝_𝑗²⟶2𝜎²_ucif𝑝_𝑖⟶𝑝_𝑗orboth𝑝_𝑖and𝑝_𝑗≥𝑝_upper,2𝜎²_uc+𝜎²_𝑝if𝑝_𝑖⟶𝑝_min,𝑝_𝑗≥𝑝_upper,𝑖,𝑗=1,2,3,…,𝑁,𝑖≠𝑗. (11) Note that (10) gives 𝑁(𝑁−1)/2 tracking relations among 𝑁 CMOS FETs. The Monte Carlo SPICE model for channel length is𝐿_𝑖=𝐿₀+𝐺₀𝜎_cm+𝑔_𝑖𝜎_uc+𝜎_𝑝𝐺₃cos𝐹₂𝑝_𝑖+𝜎_𝑝𝐺₄sin𝐹₂𝑝_𝑖,𝑖=1,2,3,…,𝑁, (12a) with 𝐹₂𝑝_𝑖=𝜋lnmin𝑝_𝑖,𝑝_upper/𝑝_min2ln𝑝_upper/𝑝_min. (12b) Using Monte Carlo model (12a)-(12b), one sees that requirement (8) is satisfied and so is requirement (9). Also using model (12a)-(12b), 𝑁(𝑁−1)/2 tracking relations among 𝑁 channel lengths are now𝐿_𝑖−𝐿_𝑗²=2𝜎²_uc+4𝜎²_𝑝sin²12𝐹₂𝑝_𝑖−12𝐹₂𝑝_𝑗=2𝜎²_uc+4𝜎²_𝑝×sin²𝜋lnmin𝑝_𝑖,𝑝_upper/min𝑝_𝑗,𝑝_upper4ln𝑝_upper/𝑝_min,𝑖,𝑗=1,2,3,…,𝑁,𝑖≠𝑗. (13) Comparing (13) with (10), one gets an explicit expression of the function 𝑓₂(𝑝_𝑖/𝑝_𝑗). There is no matrix, no eigenvalues, and no eigenvectors in Monte Carlo model (12a)-(12b). The Monte Carlo model (12a)-(12b) applies to other device/circuit tracking/ACV problems in which tracking between any two devices/circuits among a group of devices/circuits is a function of the ratio of two parameter values associated with the two devices/circuits.

2.3. Modeling the Effect of Across-Field Distance on FET Channel Length’s Tracking

The same FET in multiple (𝑁) copies of a large macro (say, a gate array) placed randomly on a chip will have the same poly density and the same gate pitch. Each FET has identical single-device tolerance (covering all lots). The tracking between any two FETs is a function of the distance between them. When two FETs are next to each other, their channel lengths are more likely to be the same (on a given chip). When two FETs are some distance apart, their channel lengths are more likely to be different (on a given chip). Further, when two FETs are separated beyond a correlation range, their channel lengths differ by a maximum amount statistically. Quantitatively, the characterization for a group of 𝑁 FETs goes like this𝐿_𝑖𝑥_𝑖,𝑦_𝑖=𝐿₀𝐿,𝑖=1,2,3,…,𝑁,_𝑖𝑥_𝑖,𝑦_𝑖−𝐿₀²=𝜎²_uc+𝜎²_af+𝜎²_cm≡𝜎²_𝐿𝐿,𝑖=1,2,3,…,𝑁,_𝑖𝑥_𝑖,𝑦_𝑖−𝐿_𝑗𝑥_𝑗,𝑦_𝑗²⟶2𝜎²_ucif𝑥_𝑖⟶𝑥_𝑗,𝑦_𝑖⟶𝑦_𝑗,𝐿𝑖,𝑗=1,2,3,…,𝑁,𝑖≠𝑗,_𝑖𝑥_𝑖,𝑦_𝑖−𝐿_𝑗𝑥_𝑗,𝑦_𝑗²⟶2𝜎²_uc+𝜎²_afif𝑥_𝑖−𝑥_𝑗≥𝑆_𝑥,𝑦_𝑖−𝑦_𝑗≥𝑆_𝑦,𝐿𝑖,𝑗=1,2,3,…,𝑁,𝑖≠𝑗,_𝑖𝑥_𝑖,𝑦_𝑖−𝐿_𝑗𝑥_𝑗,𝑦_𝑗²=𝑓₃𝑥_𝑖𝑗,𝑦_𝑖𝑗,𝑖,𝑗=1,2,3,…,𝑁,𝑖≠𝑗, (14a)(14b)(14c)(14d)(14e)with𝑥_𝑖𝑗=𝑥_𝑖−𝑥_𝑗,𝑦_𝑖𝑗=𝑦_𝑖−𝑦_𝑗, (15) where 𝜎_af is a component of ACLV variation that is associated with across-field variations on a chip. Notice that (14e) gives 𝑁(𝑁−1)/2 tracking relations among 𝑁 FETs. We use the physical location (𝑥,𝑦) of each FET as two model instance parameters. Our elegant and compact Monte Carlo model is 𝐿_𝑖=𝐿₀+𝐺₀𝜎_cm+𝑔_𝑖𝜎_uc+𝜎_af𝑄_𝑥𝑥_𝑖;𝑘𝑄_𝑦𝑦_𝑖;𝑘,𝑖=1,2,3,…,𝑁, (16) with𝑄_𝑥𝑥_𝑖=1+√2𝑐_𝑥2𝐺_1,𝑘cos𝜋𝑥_𝑖2𝑆_𝑥+𝐺_2,𝑘sin𝜋𝑥_𝑖2𝑆_𝑥+1−√2𝑐_𝑥2𝐺_3,𝑘cos3𝜋𝑥_𝑖2𝑆_𝑥+𝐺_4,𝑘sin3𝜋𝑥_𝑖2𝑆_𝑥,𝑄_𝑦𝑦_𝑖=1+√2𝑐_𝑦2𝐺_5,𝑘cos𝜋𝑦_𝑖2𝑆_𝑦+𝐺_6,𝑘sin𝜋𝑦_𝑖2𝑆_𝑦+1−√2𝑐_𝑦2𝐺_7,𝑘cos3𝜋𝑦_𝑖2𝑆_𝑦+𝐺_8,𝑘sin3𝜋𝑦_𝑖2𝑆_𝑦,14√2≤𝑐_𝑥≤12√2,14√2≤𝑐_𝑦≤12√2, (17a)(17b)where (𝑥_𝑖,𝑦_𝑖) is the coordinate of the 𝑖th FET, and 𝑘 is a group index. Notice that other FET’s locations are not needed when net listing the 𝑖th FET. Relations (14a) and (14b) on single FET’s channel length are satisfied. 𝑁(𝑁−1)/2 tracking relations among 𝑁 channel lengths are found from (16) and (17a), 𝐿_𝑖−𝐿_𝑗²=2𝜎²_uc+2𝜎²_af1−ℎ_𝑥𝑥_𝑖𝑗ℎ_𝑦𝑦_𝑖𝑗,𝑖,𝑗=1,2,3,…,𝑁,𝑖≠𝑗, (18a) when 𝐿_𝑖 and 𝐿_𝑗 belong to a same group (i.e., same 𝑘), and 𝐿_𝑖−𝐿_𝑗²=2𝜎²_uc+2𝜎²_af,𝑖,𝑗=1,2,3,…,𝑁,𝑖≠𝑗, (18b)when 𝐿_𝑖 and 𝐿_𝑗 belong to different groups. In (18a), ℎ_𝑥𝑥_𝑖𝑗=1+√2𝑐_𝑥2cos𝜋𝑥_𝑖𝑗2𝑆_𝑥+1−√2𝑐_𝑥2cos3𝜋𝑥_𝑖𝑗2𝑆_𝑥,ℎ_𝑦𝑦_𝑖𝑗=1+√2𝑐_𝑦2cos𝜋𝑦_𝑖𝑗2𝑆_𝑦+1−√2𝑐_𝑦2cos3𝜋𝑦_𝑖𝑗2𝑆_𝑦. (19) Once again, there is no matrix, no eigenvalues, and no eigenvectors in Monte Carlo model (16). 𝑁(𝑁−1)/2 correlation coefficients among 𝑁 channel lengths are𝐶𝐿_𝑖,𝐿_𝑗𝐿=1−^𝑖−𝐿_𝑗²2𝜎²_𝐿=𝜎²_cm+𝜎²_afℎ_𝑥𝑥_𝑖𝑗ℎ_𝑦𝑦_𝑖𝑗𝜎²_𝐿,𝑖,𝑗=1,2,3,…,𝑁,𝑖≠𝑗. (20) When both chip mean variation and uncorrelated variation are gone, the correlation coefficient becomes directly proportional to the product of ℎ_𝑥 and ℎ_𝑦, 𝐶𝐿_𝑖,𝐿_𝑗=ℎ_𝑥𝑥_𝑖𝑗ℎ_𝑦𝑦_𝑖𝑗,when𝜎_cm=𝜎_uc=0. (21) The spatial correlation function (21) is plotted in Figure 1. The parameter 𝑆_𝑥 (𝑆_𝑦) is the ACV correlation range in the 𝑥 (𝑦) direction, ℎ_𝑥±𝑆_𝑥=0,ℎ_𝑦±𝑆_𝑦=0. (22) The meaning of parameters 𝑐_𝑥 and 𝑐_𝑦 is revealed by these relations,ℎ_𝑥±12𝑆_𝑥=𝑐_𝑥,ℎ_𝑦±12𝑆_𝑦=𝑐_𝑦. (23) In terms of correlation coefficient, it says that𝐶𝐿_𝑖,𝐿_𝑗=𝑐_𝑥,when𝜎_cm=𝜎_uc𝑥=0,_𝑖𝑗=12𝑆_𝑥,𝑦_𝑖𝑗𝑐=0,_𝑦,when𝜎_cm=𝜎_uc𝑦=0,_𝑖𝑗=12𝑆_𝑦,𝑥_𝑖𝑗=0. (24) Namely, parameter 𝑐_𝑥 (𝑐_𝑦) is the correlation coefficient at half the ACV correlation range 𝑆_𝑥 (𝑆_𝑦). For a given characterization of spatial correlation, the values of 𝑐_𝑥 and 𝑐_𝑦 can be chosen within the range of relation (17b) (see Figure 1). [If 𝑐_𝑥 is smaller than √2/4, however, the ACV correlation function ℎ_𝑥(𝑥_𝑖𝑗) will become negative (which is unlikely physically) before the separation  |𝑥_𝑖𝑗| reaches the correlation range 𝑆_𝑥.] When the separation |𝑥_𝑖𝑗| is larger than the correlation range 𝑆_𝑥, the ACV correlation function ℎ_𝑥(𝑥_𝑖𝑗) will become either negative or will increase with increasing |𝑥_𝑖𝑗|. Thus, when two or more devices are separated more than an ACV correlation range, they should be placed into different groups.

Figure 1 

Spatial correlation function (21) versus 𝑥𝑖𝑗/𝑆𝑥 at 𝑦𝑖𝑗=0.

At a smaller separation, tracking relation (18a) reduces to Pelgrom’s characterization on device’s distance-dependent mismatch [10],𝐿_𝑖−𝐿_𝑗²≈2𝜎²_uc+𝑥²_𝑖𝑗+𝑦²_𝑖𝑗𝜋²𝜎²_af5−4√2𝑐_𝑥4𝑆²_𝑥, (25) when 𝑆_𝑥=𝑆_𝑦,𝑐_𝑥=𝑐_𝑦,|𝑥_𝑖𝑗|≪2𝑆_𝑥/3𝜋,|𝑦_𝑖𝑗|≪2𝑆_𝑦/3𝜋.

Namely, the variance of the channel length difference is the sum of a constant term and a second term which is proportional to the square of the separation between two devices.

2.4. Modeling Several ACV Effects on FET Channel Length’s Tracking Simultaneously

Combining the above solutions, we can model several ACV effects on FET channel length’s variations simultaneously. For example, for the following tracking characterization among 𝑁 CMOS FET’s channel lengths:𝐿_𝑖𝑧_𝑖;𝑝_𝑖;𝑥_𝑖,𝑦_𝑖=𝐿₀𝐿,𝑖=1,2,3,…,𝑁,_𝑖𝑧_𝑖;𝑝_𝑖;𝑥_𝑖,𝑦_𝑖−𝐿₀²=𝜎²_𝑢𝑐+𝜎²_𝑑+𝜎²_𝑝+𝜎²_af+𝜎²_cm≡𝜎²_𝐿,tot𝐿,𝑖=1,2,3,…,𝑁,_𝑖𝑧_𝑖;𝑝_𝑖;𝑥_𝑖,𝑦_𝑖−𝐿_𝑗𝑧_𝑖;𝑝_𝑖;𝑥_𝑗,𝑦_𝑗²=2𝜎²_𝑢𝑐+4𝜎²_𝑑sin²𝜋𝑧_𝑖−𝑧_𝑗4𝑧_max−𝑧_min+4𝜎²_𝑝sin²𝜋ln𝑝_𝑖/𝑝_𝑗4ln𝑝_max/𝑝_min+2𝜎²_af1−ℎ_𝑥𝑥_𝑖𝑗ℎ_𝑦𝑦_𝑖𝑗𝑓₃𝑥_𝑖𝑗,𝑦_𝑖𝑗,𝑖,𝑗=1,2,3,…,𝑁,𝑖≠𝑗, (26) with𝑧_min≤𝑧_𝑖,𝑧_𝑗≤𝑧_max,𝑝_min≤𝑝_𝑖,𝑝_𝑗≤𝑝_max,𝑖,𝑗=1,2,3,…,𝑁, (27) our overall compact Monte Carlo model is 𝐿_𝑖=𝐿₀+𝐺₀𝜎_cm+𝑔_𝑖𝜎_uc+𝐺₁𝜎_𝑑𝜋𝑧cos^𝑖−𝑧_min2𝑧_max−𝑧_min+𝐺₂𝜎_𝑑𝜋𝑧sin^𝑖−𝑧_min2𝑧_max−𝑧_min+𝜎_𝑝𝐺₃𝑝cos𝜋ln_𝑖/𝑝_min2ln𝑝_max/𝑝_min+𝜎_𝑝𝐺₄𝑝sin𝜋ln_𝑖/𝑝_min2ln𝑝_max/𝑝_min+𝜎_af𝑄_𝑥𝑥_𝑖;𝑘𝑄_𝑦𝑦_𝑖;𝑘,𝑖=1,2,3,…,𝑁. (28)𝑁(𝑁−1)/2 correlation coefficients among 𝑁 channel lengths are𝐶𝐿_𝑖,𝐿_𝑗𝐿=1−^𝑖−𝐿_𝑗²𝜎²_𝐿,tot=1𝜎²_𝐿,tot𝜎²_cm+𝜎²_𝑑𝜋𝑧cos^𝑖−𝑧_𝑗2𝑧_max−𝑧_min+𝜎²_𝑝𝑝cos𝜋ln_𝑖/𝑝_𝑗2ln𝑝_max/𝑝_min+𝜎²_afℎ_𝑥𝑥_𝑖𝑗ℎ_𝑦𝑦_𝑖𝑗,𝑖,𝑗=1,2,3,…,𝑁,𝑖≠𝑗. (29)

3. Summary

We have presented, for the first time, a novel method to model simultaneous tracking (or, say, correlation) among multiple FETs (while undergoing ACLV) at any poly density, any gate pitch, and any physical location in a compact Monte Carlo model, suitable for SPICE simulations. Without using commonly used matrix representation and associated eigen solutions, we have shown a set of very compact Monte Carlo models which simultaneously give 𝑁(𝑁−1)/2 tracking relations among 𝑁 semiconductor transistors versus one or more environment parameters, such as poly density, gate pitch, and/or physical location. At smaller separations, our modeled tracking relation versus physical location reduces to Pelgrom’s characterization on device’s distance-dependent mismatch.

Acknowledgment

The author would like to thank IBM management for support.