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Active and Passive Electronic Components
Volume 2011 (2011), Article ID 684954, 6 pages
http://dx.doi.org/10.1155/2011/684954
Research Article

Modeling of Transistor's Tracking Behavior in Compact Models

IBM Semiconductor Research and Development Center, System and Technology Group, Mail Stop 972F, 1000 River Street, Essex Junction, VT 05452, USA

Received 1 October 2010; Accepted 17 November 2010

Academic Editor: Jia Feng

Copyright © 2011 Ning Lu. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Abstract

We present a novel method to model the tracking behavior of semiconductor transistors undergoing across-chip variations in a compact Monte Carlo model for SPICE simulations and show an enablement of simultaneous tracking relations among transistors on a chip at any poly density, any gate pitch, and any physical location for the first time. At smaller separations, our modeled tracking relation versus physical location reduces to Pelgrom's characterization on device's distance-dependent mismatch. Our method is very compact, since we do not use a matrix or a set of eigen solutions to represent correlations among transistors.

1. Introduction

As semiconductor feature size decreases, the statistical variations in circuit’s characteristic, caused by statistical variations in semiconductor processes, become increasingly severe. There have been many studies on the characterization, simulation, and modeling of such statistical variations, especially on interdie and intradie/across-chip variations and device tracking behavior in recent years [19]. In a statistical description of a process, device, or circuit’s variability, one important aspect is the modeling of across-chip variations (ACV) or device tracking in a SPICE model. In this paper, we present a novel method to model the tracking behavior of semiconductor transistors undergoing across-chip variations in a compact Monte Carlo model for SPICE simulations, and show an enablement of simultaneous tracking relations among transistors on a chip at any poly density, any gate pitch, and any physical location for the first time. At smaller separations, our modeled tracking relation versus physical location reduces to Pelgrom’s characterization on device’s distance-dependent mismatch. Our method is very compact, since we do not use a matrix or a set of eigen solutions to represent correlations among transistors.

2. Modeling of FET’s Tracking Behavior

2.1. Modeling the Effect of Polysilicon Density on FET Channel Length’s Tracking

Field effect transistor (FET) channel length’s tracking relations are impacted by differences in poly pattern density. Poly pattern density is defined as the percent of total poly area within a given area (say, an area of 200 μm × 200 μm), which is a relatively small area from a wafer polish viewpoint but is very large compared to the size of a transistor. For all poly densities (within an allowed range; say, between and ), the standard deviation of a single transistor’s channel length is a constant (covering all lots), independent of the poly pattern density around it. However, the tracking in channel length between two FETs is impacted by the difference between two poly density values around each of them. When two FETs have similar poly density values, their channel lengths are more likely to be the same on a given chip. On the other hand, when two FETs have different poly densities around each of them, their channel lengths are more likely to be different on a given chip. Quantitatively, a characterization goes like the following. For a group of FETs in a small area with a same gate pitch but different poly densities, (a) all FETs have the same nominal channel length , independent of poly density around each FET, where is the poly density around the th FET; (b) all FETs have the same variance for channel length, independent of poly density around each FET, where is completely uncorrelated part of channel length variations, is chip-mean (completely correlated) part of variations, and represents a partially correlated ACLV component that is associated with poly density’s change on a chip; (c) the tracking between the channel length of the th FET and the channel length of the th FET, however, is a function of the difference between the poly density around the th FET and the poly density around the th FET, with two limiting values, Notice that (3) gives tracking relations among FETs. In (3) and (4), poly densities are bounded at both ends, Also in (3), is a continuous and symmetric function of and increases monotonically with . It is very important to characterize both single-device’s tolerance and the tracking/mismatch between two devices separately. It is a challenge to find a stochastic function which leads to tracking behavior (3) for three or more FETs () simultaneously. A difficulty lies in this: how to net list the th FET without entering all other FETs information into the model call for the th FET? There are only a few solutions.

We use polysilicon density as a model instance parameter in an FET’s compact model. The Monte Carlo model for improved ACLV modeling is In (6) and in the rest of the paper, each of is an independent stochastic variable of mean zero and standard deviation one. For a pre-layout (i.e., schematic) FET model in which poly density is not known at net list time, can be a random value between and . Using Monte Carlo model (6), it is easy to see that requirement (1) is satisfied and so is requirement (2). Also using model (6), tracking relations among FET’s channel lengths are found to be which depends on the poly density difference only. Comparing (7) with (3), one gets an explicit expression of the function . We want to point out that there is no matrix, no eigenvalues, and no eigenvectors in Monte Carlo model (6). The Monte Carlo model (6) applies to other device/circuit tracking/ACV problems in which tracking between any two devices/circuits among a group of devices/circuits is a function of the difference of two parameter values associated with the two devices/circuits.

2.2. Modeling the Effect of Gate Pitch on FET Channel Length’s Tracking

In a given semiconductor technology, there is a minimum gate pitch (), which is related to the lithography print capability used for the semiconductor technology. Note that a gate pitch is the sum of poly width (i.e., FET channel’s design length) and poly-to-poly space. At the minimum gate pitch, poly width is typically at the minimum poly width for the given semiconductor technology. Besides a minimum gate pitch (), other larger gate pitch values (say, twice of , four times of , etc.) are also allowed. At a given larger gate pitch, poly width can take several different values. In other words, even at a single transistor’s layout level, there may not be any relation between a gate pitch and a local poly density. Since poly pattern density is an averaged value over a large area of, say, 200 μm × 200 μm, gate pitch and poly density are treated as two independent quantities. Often, a semiconductor company characterizes the effect of gate pitch and the effect of poly density separately. A characterization of the single channel length’s tolerance and the tracking between two channel lengths goes like the following. For a group of CMOS FETs within a small area (say, within an area of 200 μm × 200 μm), there is a fixed value for poly pattern density, but these CMOS FETs can have different gate pitches. Quantitatively, (a) all FETs have the same nominal channel length , independent of gate pitch , where is the gate pitch of the th FET. (b) All FETs have the same variance for channel length, independent of gate pitch , whereis a component of ACLV variation that is associated with gate pitch variations on a chip. And (c) the tracking between the channel length of the th FET and the channel length of the th FET, however, is a function of the ratio between the gate pitch of the th FET and the gate pitch of the th FET, with two limiting values, Note that (10) gives tracking relations among CMOS FETs. The Monte Carlo SPICE model for channel length is with Using Monte Carlo model (12a)-(12b), one sees that requirement (8) is satisfied and so is requirement (9). Also using model (12a)-(12b), tracking relations among channel lengths are now Comparing (13) with (10), one gets an explicit expression of the function . There is no matrix, no eigenvalues, and no eigenvectors in Monte Carlo model (12a)-(12b). The Monte Carlo model (12a)-(12b) applies to other device/circuit tracking/ACV problems in which tracking between any two devices/circuits among a group of devices/circuits is a function of the ratio of two parameter values associated with the two devices/circuits.

2.3. Modeling the Effect of Across-Field Distance on FET Channel Length’s Tracking

The same FET in multiple () copies of a large macro (say, a gate array) placed randomly on a chip will have the same poly density and the same gate pitch. Each FET has identical single-device tolerance (covering all lots). The tracking between any two FETs is a function of the distance between them. When two FETs are next to each other, their channel lengths are more likely to be the same (on a given chip). When two FETs are some distance apart, their channel lengths are more likely to be different (on a given chip). Further, when two FETs are separated beyond a correlation range, their channel lengths differ by a maximum amount statistically. Quantitatively, the characterization for a group of FETs goes like thiswith where is a component of ACLV variation that is associated with across-field variations on a chip. Notice that (14e) gives tracking relations among FETs. We use the physical location () of each FET as two model instance parameters. Our elegant and compact Monte Carlo model is withwhere () is the coordinate of the th FET, and is a group index. Notice that other FET’s locations are not needed when net listing the th FET. Relations (14a) and (14b) on single FET’s channel length are satisfied. tracking relations among channel lengths are found from (16) and (17a), when and belong to a same group (i.e., same ), and when and belong to different groups. In (18a), Once again, there is no matrix, no eigenvalues, and no eigenvectors in Monte Carlo model (16). correlation coefficients among channel lengths are When both chip mean variation and uncorrelated variation are gone, the correlation coefficient becomes directly proportional to the product of and , The spatial correlation function (21) is plotted in Figure 1. The parameter () is the ACV correlation range in the () direction, The meaning of parameters and is revealed by these relations, In terms of correlation coefficient, it says that Namely, parameter () is the correlation coefficient at half the ACV correlation range (). For a given characterization of spatial correlation, the values of and can be chosen within the range of relation (17b) (see Figure 1). [If is smaller than , however, the ACV correlation function will become negative (which is unlikely physically) before the separation   reaches the correlation range .] When the separation is larger than the correlation range , the ACV correlation function will become either negative or will increase with increasing . Thus, when two or more devices are separated more than an ACV correlation range, they should be placed into different groups.

684954.fig.001
Figure 1: Spatial correlation function (21) versus at .

At a smaller separation, tracking relation (18a) reduces to Pelgrom’s characterization on device’s distance-dependent mismatch [10], when .

Namely, the variance of the channel length difference is the sum of a constant term and a second term which is proportional to the square of the separation between two devices.

2.4. Modeling Several ACV Effects on FET Channel Length’s Tracking Simultaneously

Combining the above solutions, we can model several ACV effects on FET channel length’s variations simultaneously. For example, for the following tracking characterization among CMOS FET’s channel lengths: with our overall compact Monte Carlo model is correlation coefficients among channel lengths are

3. Summary

We have presented, for the first time, a novel method to model simultaneous tracking (or, say, correlation) among multiple FETs (while undergoing ACLV) at any poly density, any gate pitch, and any physical location in a compact Monte Carlo model, suitable for SPICE simulations. Without using commonly used matrix representation and associated eigen solutions, we have shown a set of very compact Monte Carlo models which simultaneously give tracking relations among semiconductor transistors versus one or more environment parameters, such as poly density, gate pitch, and/or physical location. At smaller separations, our modeled tracking relation versus physical location reduces to Pelgrom’s characterization on device’s distance-dependent mismatch.

Acknowledgment

The author would like to thank IBM management for support.

References

  1. C. C. McAndrew and P. G. Drennan, “Unified statistical modeling for circuit simulation,” in Proceedings of the International Conference on Modeling and Simulation of Microsystems (MSM '02), pp. 715–718, 2002.
  2. C. C. McAndrew and P. G. Drennan, “Device correlation: modeling using uncorrelated parameters, characterization using ratios and differences,” in Proceedings of the NSTI Nanotechnology Conference and Trade Show, vol. 3, pp. 698–702, 2006.
  3. J. Watts, N. Lu, C. Bittner, S. Grundon, and J. Oppold, “Modeling FET variation within a chip as a function of circuit design and layout choices,” in Proceedings of the NSTI Nanotechnology Conference and Trade Show, vol. 3, pp. 87–92, 2005.
  4. A. Gattiker, M. Bhushan, and M. B. Ketchen, “Data analysis techniques for CMOS technology characterization and product impact assessment,” in Proceedings of the International Test Conference, pp. 1–10, 2006.
  5. S. K. Springer, S. Lee, and S. Lee, “Modeling of variation in submicrometer CMOS ULSI technologies,” IEEE Transactions on Electron Devices, vol. 53, no. 9, pp. 2168–2177, 2006. View at Publisher · View at Google Scholar · View at Scopus
  6. Y. Ye, F. Liu, S. Nassif, and Y. Cao, “Statistical modeling and simulation of threshold variation under dopant fluctuations and line-edge roughness,” in Proceedings of the 45th Design Automation Conference (DAC '08), pp. 900–905, June 2008. View at Publisher · View at Google Scholar
  7. N. Lu, “Modeling of spatial correlations in process, device, and circuit variations,” in Proceedings of the NSTI Nanotechnology Conference and Trade Show, vol. 3, pp. 818–821, 2008.
  8. H. Onodera, “Variability modeling and impact on design,” in Proceedings of the International Electron Devices Meeting (IEDM '08), pp. 701–704, 2008.
  9. N. Lu, J. Watts, and S. K. Springer, “Elements of statistical SPICE models,” in Proceedings of theNSTI Nanotechnology Conference and Expo (NSTI-Nanotech '09), vol. 3, pp. 616–619, 2009.
  10. M. J. M. Pelgrom, A. C. J. Duinmaijer, and A. P. G. Welbers, “Matching properties of MOS transistors,” IEEE Journal of Solid-State Circuits, vol. 24, no. 5, pp. 1433–1440, 1989. View at Publisher · View at Google Scholar · View at Scopus