Proposal of High-Temperature-Operation Tolerant SOI MOSFET and Preliminary Study on Device Performance Evaluation

Omura, Yasuhisa

doi:https://doi.org/10.1155/2011/850481

Active and Passive Electronic Components

On this page

Abstract Introduction Results and Discussion Conclusion References Copyright Related Articles

Research Article | Open Access

Volume 2011 | Article ID 850481 | https://doi.org/10.1155/2011/850481

Proposal of High-Temperature-Operation Tolerant SOI MOSFET and Preliminary Study on Device Performance Evaluation

Yasuhisa Omura¹

Academic Editor: G. Ghibaudo

Received14 Jun 2011

Revised11 Jul 2011

Accepted11 Jul 2011

Published15 Sept 2011

Abstract

We propose a high-temperature-operation (HTOT) SOI MOSFET and show preliminary simulation results of its characteristics. It is demonstrated that HTOT SOI MOSFET operates safely at 700 K with no thermal instability because of its expanded effective bandgap. It is shown that its threshold voltage is higher than that of the conventional SOI MOSFET because its local thin Si regions offer an expanded effective band gap. It is shown that HTOT SOI MOSFET with 1-nm-thick local-thin Si regions is almost insensitive to temperature for (427 C). This confirms that HTOT SOI MOSFET is a promising device for future high-temperature applications.

1. Introduction

The long-term goal in integrated circuits is to lower the dimensionality of MOS transistors in order to increase the function-density and also the speed of extremely large-scale silicon-integrated circuits [1]. The necessity of the silicon-on-insulator (SOI) MOSFET is clear, given its merits of high-speed operation and low-power operation with fewer short-channel effects [2]. However, its off-leakage current is significant, even in thin SOI MOSFETs in the sub-100-nm regime [3]. The author recently proposed the tunneling barrier junction (TBJ) SOI MOSFET that offers suppressed off-leakage current [4, 5]. It has been shown that the TBJ SOI MOSFET suffers from low drive current if used at low temperatures as intended [6].

It has been demonstrated, however, that the thin SOI MOSFET is a promising device for applications that work at 300 C [1]. Its off-leakage current is still a serious problem and prevents its use at higher temperatures. When analyzing high-temperature-operation, it is anticipated that we do not need full quantum-mechanical simulations even for a thin SOI MOSFET because the influence of various carrier scattering events on the transport in the channel region is crucial; so-called thermalization is dominant in the Si material.

This paper applies the semiclassical transport model to assess the feasibility of SOI MOSFET in achieving high-temperature operation. This paper introduces the High-Temperature-Operation Tolerant (HTOT) SOI MOSFET and shows preliminary simulation results of its characteristics. A commercial 2D device simulator [7] is used to simulate the drain current characteristics throughout the study.

2. Device Structure and Simulations

A schematic of HTOT SOI MOSFET is shown in Figure 1(a). The device has an n⁺-Si gate, a thin n-type body, two thin p-type bodies, and two local-thin Si regions; it is assumed that the top SOI layer surface has (001) orientation. The gate oxide layer is 5-nm thick, buried oxide layer is 100-nm thick, thin n-type Si body and thin p-type Si body are 10-nm thick, and two local-thin Si regions are 1-nm or 2-nm thick; the local-thin Si regions are 2-nm long. n⁺-Si source and drain diffusion regions are 10-nm thick and their doping concentrations are cm⁻³; the junction is assumed to be abrupt for simplicity. P-type body has a doping concentration of cm⁻³ and n-type body has a doping concentration of cm⁻³. Gate length (L_g) is 100 nm (or 60 nm) and gate width (W) is 1 μm; n-type Si region is typically 10 nm long and p-type Si region is typically 40 nm long (20 nm long in some cases); this dimension is selected to suppress the short-channel effect. Since the Si layer is very thin in the two local-thin regions, the energy levels in these regions are distinctly quantized. Schematic band structure at V and is shown in Figure 1(b), and the effective bandgap energy () of the local-thin Si regions is larger than the nominal bandgap energy of bulk Si (E_G); its theoretical expression is given as [8] where E_n1 is the ground-state level energy of confined electrons in the conduction band and E_p1 is the ground-state level energy of confined holes in the valence band. In calculating E_G*, the temperature dependence of intrinsic bandgap energy (E_G(T)) of Si is taken into account [9].

(a)

(b)

When the confinement is along the z-axis (normal to (001) surface), the ground-state energy level of 2-fold X-valleys (E_n1) in the local-thin Si body is given by where is the effective mass of electrons for the 2-fold X-valley and is the thickness of local-thin Si region (= 2 or 1 nm). E_n1 – E_C is about 0.1 eV (~1200 K) when the local-thin Si region is 2-nm thick and about 0.2 eV when the local-thin Si region is 1-nm thick [10]; this suggests that the following consideration based on quantum mechanics is well acceptable because the maximal operation temperature assumed is 700 K.

Since it is assumed that the device works at high temperature, it is expected that semiclassical analysis can be used in the simulations, where we basically assume semiclassical hydrodynamic transport in both thin and thick bodies, and the thermionic emission model [11] is introduced to calculate the transport through the local-thin Si regions using the conventional heterojunction model. This approximation is valid except for the degenerate semiconductor. Therefore, it is expected that, at high temperatures with V, the effective energy barrier of the 2-nm-long local-thin Si region enhances thermionic conduction rather than electron tunneling. Accordingly, we apply the thermionic emission model in the present simulations. Mobility models for carrier transport comply with the following physics; Massetit model for doping dependent mobility [12], Lombardi model for mobility degradation at the Si/SiO₂ interface [13] and Canali model for mobility degradation due to velocity saturation [14]. In the present consideration, the subthreshold characteristics are focused on because the increase in the off-current is crucial for such devices at high temperature. The mobility models primarily rule the on-current, not the off-current. Therefore, it is anticipated that the mobility models assumed here do not influence significantly the present consideration.

In addition, since n-type and p-type Si regions are 10-nm thick, discreteness of electronic states is not so crucial for the semiclassical analysis. Thus, to develop an overall consideration of the transport characteristics of the HTOT SOI MOSFET, it can be concluded that the semiclassical analysis is sufficiently verifiable. In the simulation, therefore, we replace the default parameters for the ultrathin Si region with a new set of physical parameters, where the bandgap energy and the effective electron affinity are revised following (1) and (2). When confinement is applied to the HTOT SOI MOSFET, a 3.5-nm-thick local-thin Si region yields a 0.1-eV-high (about) barrier to the conduction electrons; confinement yields an identical result.

Possible fabrication process of the HTOT SOI MOSFET is introduced in Figure 2. The major processing steps are given below.(a)Shallow and narrow trenches are formed on the n-type SOI layer by the focused ion beam etching technique.(b)Surface is oxidized in a furnace tube, resulting in separation of the central n-type body.(c)Surface oxide layer is removed.(d)A thin crystalline Si layer is deposited epitaxially and surface oxide layer is formed as the gate insulator.(e)After the n-type body region is covered by resist, p-type body regions are formed by Boron ion implantation and the substrate is annealed.(f)Gate poly-Si is deposited and the gate electrode pattern is formed. As ion implantation is performed to form source and drain regions.

(a)

(b)

(c)

(d)

(e)

(f)

The fabrication process mentioned above requests challenging techniques and simulations to predict device characteristics that must also cover atomic-scale physics. The local-thin Si layer has countable atomic layers. Regarding such a thin Si layer, several articles consider the impact of Si-layer thickness on transport properties [15–20]. These articles predict the following(i)4 atomic Si layers can roughly hold a bulk band structure [15, 16];(ii)Effective mass values of conduction band electrons increase as the Si layer is thinned [17–20].

The second point [17–20] suggests that the effective barrier height of the local-thin Si layer may be overestimated. In that case, as suggested later, we should take a longer local-thin Si region to have better characteristics at high temperature.

3. Results and Discussion

3.1. Room Temperature Characteristics

In the HTOT SOI MOSFET, most carriers cannot tunnel through the insulators but can pass through the local-thin Si regions between gate oxide and barrier insulators; the barrier insulator acts as a hard barrier. Since the local-thin Si region is very narrow along the surface channel region, distinct energy quantization should be assumed in the local-thin Si region even at high temperatures because . Therefore, the bandgap of the Si region between the gate oxide layer and the barrier insulator is effectively widened which reduces the total drain current. In high-temperature environments the thermal energy of some carriers can exceed the ground-state level ( or ) in the channel. Thus, it can be expected that both the drive current and off-current of an HTOT SOI MOSFET operating at high temperatures will be larger than those of a TBJ MOSFET [4, 5], while its subthreshold swing at high temperatures is superior to that of the conventional SOI MOSFET.

Figure 3 shows I_d-V_g characteristics of a HTOT SOI MOSFET with a 40-nm long p-type region () at 300 K for various values; it is assumed that the HTOT SOI MOSFET has 1-nm-thick local-thin Si regions on both sides of the n-type Si body. It is seen that the HTOT SOI MOSFET has a subthreshold swing value of ~70 mV/dec. and ON current of about 350 A/μm at V.

I_d-V_d characteristics of the HTOT SOI MOSFET at 300 K for various conditions are shown in Figure 4 for nm. It is also assumed that the HTOT SOI MOSFET has 1-nm-thick local-thin Si regions on both sides of the n-type Si body. In order to consider conduction mechanisms, the schematic band diagram of the HTOT SOI MOSFET is shown in Figure 5 for V; arrows indicate carrier-flow paths in the energy space. Two characteristic behaviors are considered; (i) the super-linear increase in the drain current stems from the nonohmic conduction through the local-thin Si regions at the source side, (ii) the negative differential conductance at stems from the high impedance created by the local-thin Si regions at the drain side.

With regard to the I_d-V_g characteristics of the TBJ MOSFET [4, 5] under the assumption of full tunneling and ballistic transport, the drain current curve shows a kink at around the threshold voltage () and the drain current is almost constant for . In Figure 4, however, the drain current of the HTOT SOI MOSFET smoothly increases around and it increases monotonously for . This means that the drain current of the HTOT SOI MOSFET is ruled by the semiclassical mechanism.

3.2. High-Temperature Characteristics

This section discusses in detail the I-V characteristics of the HTOT MOSFET at temperatures ranging from 300 K to 700 K. The temperature dependencies of the - characteristics of the conventional SOI MOSFET with a 10-nm-thick p-type body and the HTOT SOI MOSFET with 1-nm-thick local-thin Si regions at the edges of 10-nm-thick n-type body at T = 300, 500, and 700 K are shown in Figures 6 and 7, respectively. Subthreshold swing at each temperature is also indicated in the figures. Little difference in subthreshold swing between the conventional SOI MOSFET and the HTOT SOI MOSFET is seen at T = 300 K in Figures 6 and 7. At 700 K, however, the difference in subthreshold swing is 40 mV/dec; the advantage of subthreshold swing of the HTOT SOI MOSFET is about 5%. The HTOT SOI MOSFET operates safely at 700 K with no thermal instability because of its expanded effective bandgap [8]. Thus the HTOT MOSFET is somewhat superior to the conventional SOI MOSFET in high-temperature operation. When the threshold voltage () is set to 0.3 V at the drain voltage () of 0.1 V at 700 K, the drain current of the HTOT SOI MOSFET has an on/off-dynamic range of about 1.7.

Next, device operations are discussed for the case wherein the energy levels in the 1-nm-thick local-thin Si region are quantized. When energy levels are quantized in the local-thin Si region, the effective conduction band bottom rises to the ground state energy level; consequently, the bandgap is effectively widened. When the local-thin Si region is 1-nm wide, the ground state energy level is higher by 0.26 eV than the conduction band bottom. In the following, characteristics are simulated for two cases; the ground state energy level is higher by 0.1 or 0.2 eV than the conduction band bottom. In addition, the thickness of the “hard barrier” insulator adjacent to the local-thin Si regions is changed to 10 nm in order to clarify the influence of long and narrow conduction paths on overall carrier transport. In this case, nm and nm.

- characteristics depending on temperature () for the HTOT SOI MOSFET at V are shown in Figures 8 and 9 for nm; in Figure 8, it is assumed that the ground state energy level of the local-thin Si region is higher by 0.1 eV than the conduction band bottom, and in Figure 9, it is assumed to be higher by 0.2 eV. The following points are found in Figures 8 and 9. (i) Subthreshold swing values are insensitive to the width of the local-thin-Si regions because subthreshold conduction is inherently similar to the thermionic process. (ii) Drain current at V is sensitive to the width of the local-thin Si regions as expected because the long and narrow conduction path reduces channel conductivity. When energy levels of the conduction band in the local-thin Si region are discretely quantized, the ground state level in the local-thin Si regions should be higher than the conduction band bottom of the surface-inverted p-type region. (iii) The leakage current at V is sensitive to the width of the local-thin Si regions because the electron density in the conduction band strongly depends on the “effective bandgap energy” (E_G*).

Since the bandgap energy of the local-thin Si regions is larger than that of bulk Si, the intrinsic carrier density value of the local-thin Si regions (n_i*) should be lower than that of the bulk Si (n_i) as expected by the following [8]: where and are the density of states of two-dimensional conduction-band electrons and the density of states of two-dimensional valence band holes, respectively. The density of states is a function of the effective mass; for simplicity, it is assumed the effective mass is independent of temperature. On the other hand, it is assumed that Debye length (L_D) and the intrinsic bandgap energy (E_G) is a function of temperature [9]. Equation (3) is quite valid for high temperatures because it was derived on the basis of high-temperature approximations. The conduction band of Si presents the electrons with an effective barrier height of and the thermionic emission current is controlled by the barrier of . This barrier suppresses the subtreshold leakage current at high temperatures. Therefore, the thickness and length of the local-thin Si regions is a design issue and depends on the implementation demands.

Simulated threshold voltage () and subthreshold swing (S) at drain voltage of 0.1 V are summarized in Figure 10. It is assumed that the SOI layer has a (001) Si surface. The HTOT SOI MOSFET is compared to the conventional SOI MOSFET with a 10-nm-thick SOI layer. It is assumed in Figure 10(a) that the local-thin Si regions are 2-nm thick and 2-nm long. At room temperature, both devices show almost identical characteristics; only the threshold voltage is slightly different. However, the HTOT SOI MOSFET exhibits much lower performance degradation than the conventional SOI MOSFET; mV/K and mV/dec/K for the HTOT SOI MOSFET. When threshold voltage is set to 0.3 V at 700 K, the present HTOT SOI MOSFET has superior off-leakage, by a factor of 3, to the conventional SOI MOSFET. The threshold voltage of the HTOT SOI MOSFET is higher than that of the SOI MOSFET by about 0.2 V; this is slightly larger than because electrons contributing to the threshold current should have the averaged energy slightly larger than at the threshold [21].

(a)

(b)

In Figure 10(b), simulated threshold voltage () and subthreshold swing (S) are shown at the drain voltage of 0.1 V for 1-nm-thick local-thin Si regions; the HTOT SOI MOSFET is compared to the conventional SOI MOSFET with a 10-nm-thick SOI layer. The results demonstrate that the HTOT SOI MOSFET has outstanding performance: mV/K and mV/dec/K. Subthreshold swing of the HTOT SOI MOSFET is about 178 mv/dec at 700 K (427 C). It should be noted that the HTOT SOI MOSFET with 1-nm-thick local-thin Si regions is almost insensitive to temperature for K (427 C). The mechanism is the same as that described previously.

Finally, versus characteristics of the HTOT SOI MOSFET are shown in Figure 11 at V. Slopes of curves range from −5 to −8. The reduction in on-current values at high temperatures is due to mobility degradation, and the drastic increase in off-current at high temperatures is due to the thermionic emission process. It is seen that the difference in local thin Si region thickness primarily impacts the on-current value (), and that the off-current value () is not so sensitive to the local-thin Si region thickness; these are important aspects of the HTOT SOI MOSFET from the viewpoint of device design.

4. Conclusion

This paper proposed the High-Temperature-Operation Tolerant (HTOT) SOI MOSFET and demonstrated preliminary device simulation results of its characteristics.

The HTOT SOI MOSFET has local-thin Si regions and operates safely at 700 K with no thermal instability because of its expanded effective band gap. A HTOT SOI MOSFET with 2-nm-thick local-thin body regions exhibits much lower performance degradation than the conventional SOI MOSFET; mV/K and mV/dec/K for the HTOT SOI MOSFET. Subthreshold swing of the HTOT SOI MOSFET is about 180 mv/dec at 700 K (427 C). Threshold voltage of the HTOT SOI MOSFET is higher than that of SOI MOSFET by about 0.2 V because the local-thin Si regions offer an expanded effective band gap.

An HTOT SOI MOSFET with 1-nm-thick local-thin Si regions shows outstanding performance: mV/K and mV/dec/K. Subthreshold swing of the HTOT SOI MOSFET is about 178 mv/dec at 700 K (427 C). Therefore, the HTOT SOI MOSFET is a promising device for future high-temperature applications when its device parameters are appropriately optimized.

Acknowledgment

The author wishes to express his thanks to Mr. H. Nakajima, presently Canon Corp., Japan, for his assistance with the device simulations.

References

J.-P. Colinge, Silicon-On-Insulator Technology: Materials to VLSIs, Kluwer Academic Publishers, Boston, Mass, USA, 2nd edition, 1997.
Y. Omura, “Silicon-on-insulator (SOI) MOSFET structure for sub-50-nm channel regime,” in Proceedings of the 10th International Symposium on SOI Technology and Development, vol. PV2001-3, pp. 205–210, Electrochemical society, 2001.
View at: Google Scholar
H. Nakajima, S. I. Yanagi, K. Komiya, and Y. Omura, “Off-leakage and drive current characteristics of sub-100-nm SOI MOSFETs and impact of quantum tunnel current,” IEEE Transactions on Electron Devices, vol. 49, no. 10, pp. 1775–1782, 2002.
View at: Publisher Site | Google Scholar
Y. Omura, “A tunneling-barrier junction MOSFET on SOI substrates with a suppressed short-channel effect for the ultimate device structure,” in Proceedings of the 10th International Symposium on SOI Technology and Development, vol. PV2001-3, pp. 451–456, Electrochemical society, 2001.
View at: Google Scholar
H. Nakajima, A. Kawamura, K. Komiya, and Y. Omura, “Simulation models for silicon-on-insulator tunneling-barrier-junction metal-oxide-semiconductor field-effect transistor and performance perspective,” Japanese Journal of Applied Physics, Part 1, vol. 42, no. 3, pp. 1206–1211, 2003.
View at: Google Scholar
H. Nakajima, A. Kawamura, K. Komiya, and Y. Omura, “Simulation models for silicon-on-insulator tunneling-barrier-junction metal-oxide-semiconductor field-effect transistor and performance perspective,” Japanese Journal of Applied Physics, Part 1, vol. 42, no. 3, pp. 1206–1211, 2003.
View at: Google Scholar
ISE-TCAD, “Integrated System Engineering Inc., presently, Synopsys Inc.,” Release Manual, V8.0, 2003.
View at: Google Scholar
Y. Omura, T. Ishiyama, M. Shoji, and K. Izumi, “Quantum Mechanical Transport Characteristics in Ultimately Miniaturized MOSFETs/SIMOX,” in Proceedings of the 10th International Symposium on SOI Technology and Development, vol. PV96-3, pp. 199–205, Electrochemical society, 1996.
View at: Google Scholar
S. M. Sze, Physics of Semiconductor Devices, John Wiley & Sons, New York, NY, USA, 2nd edition, 1981.
Y. Omura, S. Horiguchi, M. Tabe, and K. Kishi, “Quantum-mechanical effects on the threshold voltage of ultrathin-SOI nMOSFET's,” IEEE Electron Device Letters, vol. 14, no. 12, pp. 569–571, 1993.
View at: Publisher Site | Google Scholar
D. Schroeder, Modeling of Interface Carrier Transport for Device Simulations, Springer, Wien, Austria, 1994.
G. Masetti, M. Severi, and S. Solmi, “Modeling Of Carrier Mobility Against Carrier Concentration In Arsenic-, Phosphorus-, and boron-doped silicon,” IEEE Transactions on Electron Devices, vol. ED-30, no. 7, pp. 764–769, 1983.
View at: Google Scholar
C. Lombardi, S. Manzini, A. Saporito, and M. Vanzi, “Physically based mobility model for numerical simulation of nonplanar devices,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 7, no. 11, pp. 1164–1171, 1988.
View at: Publisher Site | Google Scholar
C. Canali, G. Majni, R. Minder, and G. Ottaviani, “Electron and hole drift velocity measurements in silicon and their empirical relation to electric field and temperature,” IEEE Transactions on Electron Devices, vol. ED-22, no. 11, pp. 1045–1047, 1975.
View at: Google Scholar
S. Wakui, J. Nakamura, and A. Natori, “Atomic scale dielectric constant near the SiO2 /Si (001) interface,” Journal of Vacuum Science and Technology B, vol. 26, no. 4, pp. 1579–1584, 2008.
View at: Publisher Site | Google Scholar
H. Kageshima and A. Fujiwara, “First-principles study on inversion layer properties of double-gate atomically thin silicon channels,” Applied Physics Letters, vol. 93, no. 4, Article ID 043516, 2008.
View at: Publisher Site | Google Scholar
K. Nehari, N. Cavassilas, J. L. Autran, M. Bescond, D. Munteanu, and M. Lannoo, “Influence of band structure on electron ballistic transport in silicon nanowire MOSFET's: an atomistic study,” Solid-State Electronics, vol. 50, no. 4, pp. 716–721, 2006.
View at: Publisher Site | Google Scholar
P. V. Sushko and A. L. Shluger, “Electronic structure of insulator-confined ultra-thin Si channels,” Microelectronic Engineering, vol. 84, no. 9-10, pp. 2043–2046, 2007.
View at: Publisher Site | Google Scholar
M. De Michielis, D. Esseni, Y. L. Tsang et al., “A semianalytical description of the hole band structure in inversion layers for the physically based modeling of pMOS transistors,” IEEE Transactions on Electron Devices, vol. 54, no. 9, pp. 2164–2173, 2007.
View at: Publisher Site | Google Scholar
Y. Omura, “Extension of analytical model for conduction band nonparabolicity to transport analysis of nanoscale metal-oxide-semiconductor field-effect transistor,” Journal of Applied Physics, vol. 105, no. 1, Article ID 014310, 2009.
View at: Publisher Site | Google Scholar
Y. Tamara and Y. Omura, “Empirical quantitative Modeling of threshold voltage of sub-50-nm double-gate SOI MOSFET’s,” Japanese Journal of Applied Physics, vol. 45, pp. 3074–3078, 2006.
View at: Publisher Site | Google Scholar

Copyright

Copyright © 2011 Yasuhisa Omura. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

PDF Download Citation

Download other formats

Order printed copies

Views

1298

Downloads

1191

Citations