About this Journal Submit a Manuscript Table of Contents
Active and Passive Electronic Components
Volume 2011 (2011), Article ID 850481, 8 pages
http://dx.doi.org/10.1155/2011/850481
Research Article

Proposal of High-Temperature-Operation Tolerant SOI MOSFET and Preliminary Study on Device Performance Evaluation

ORDIST, Graduate School of Engineering Science, Kansai University, 3-3-35 Yamate-cho, Suita, Osaka 564-8680, Japan

Received 14 June 2011; Revised 11 July 2011; Accepted 11 July 2011

Academic Editor: G. Ghibaudo

Copyright © 2011 Yasuhisa Omura. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Linked References

  1. J.-P. Colinge, Silicon-On-Insulator Technology: Materials to VLSIs, Kluwer Academic Publishers, Boston, Mass, USA, 2nd edition, 1997.
  2. Y. Omura, “Silicon-on-insulator (SOI) MOSFET structure for sub-50-nm channel regime,” in Proceedings of the 10th International Symposium on SOI Technology and Development, vol. PV2001-3, pp. 205–210, Electrochemical society, 2001.
  3. H. Nakajima, S. I. Yanagi, K. Komiya, and Y. Omura, “Off-leakage and drive current characteristics of sub-100-nm SOI MOSFETs and impact of quantum tunnel current,” IEEE Transactions on Electron Devices, vol. 49, no. 10, pp. 1775–1782, 2002. View at Publisher · View at Google Scholar · View at Scopus
  4. Y. Omura, “A tunneling-barrier junction MOSFET on SOI substrates with a suppressed short-channel effect for the ultimate device structure,” in Proceedings of the 10th International Symposium on SOI Technology and Development, vol. PV2001-3, pp. 451–456, Electrochemical society, 2001.
  5. H. Nakajima, A. Kawamura, K. Komiya, and Y. Omura, “Simulation models for silicon-on-insulator tunneling-barrier-junction metal-oxide-semiconductor field-effect transistor and performance perspective,” Japanese Journal of Applied Physics, Part 1, vol. 42, no. 3, pp. 1206–1211, 2003. View at Scopus
  6. H. Nakajima, A. Kawamura, K. Komiya, and Y. Omura, “Simulation models for silicon-on-insulator tunneling-barrier-junction metal-oxide-semiconductor field-effect transistor and performance perspective,” Japanese Journal of Applied Physics, Part 1, vol. 42, no. 3, pp. 1206–1211, 2003. View at Scopus
  7. ISE-TCAD, “Integrated System Engineering Inc., presently, Synopsys Inc.,” Release Manual, V8.0, 2003.
  8. Y. Omura, T. Ishiyama, M. Shoji, and K. Izumi, “Quantum Mechanical Transport Characteristics in Ultimately Miniaturized MOSFETs/SIMOX,” in Proceedings of the 10th International Symposium on SOI Technology and Development, vol. PV96-3, pp. 199–205, Electrochemical society, 1996.
  9. S. M. Sze, Physics of Semiconductor Devices, John Wiley & Sons, New York, NY, USA, 2nd edition, 1981.
  10. Y. Omura, S. Horiguchi, M. Tabe, and K. Kishi, “Quantum-mechanical effects on the threshold voltage of ultrathin-SOI nMOSFET's,” IEEE Electron Device Letters, vol. 14, no. 12, pp. 569–571, 1993. View at Publisher · View at Google Scholar · View at Scopus
  11. D. Schroeder, Modeling of Interface Carrier Transport for Device Simulations, Springer, Wien, Austria, 1994.
  12. G. Masetti, M. Severi, and S. Solmi, “Modeling Of Carrier Mobility Against Carrier Concentration In Arsenic-, Phosphorus-, and boron-doped silicon,” IEEE Transactions on Electron Devices, vol. ED-30, no. 7, pp. 764–769, 1983. View at Scopus
  13. C. Lombardi, S. Manzini, A. Saporito, and M. Vanzi, “Physically based mobility model for numerical simulation of nonplanar devices,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 7, no. 11, pp. 1164–1171, 1988. View at Publisher · View at Google Scholar · View at Scopus
  14. C. Canali, G. Majni, R. Minder, and G. Ottaviani, “Electron and hole drift velocity measurements in silicon and their empirical relation to electric field and temperature,” IEEE Transactions on Electron Devices, vol. ED-22, no. 11, pp. 1045–1047, 1975. View at Scopus
  15. S. Wakui, J. Nakamura, and A. Natori, “Atomic scale dielectric constant near the SiO2 /Si (001) interface,” Journal of Vacuum Science and Technology B, vol. 26, no. 4, pp. 1579–1584, 2008. View at Publisher · View at Google Scholar · View at Scopus
  16. H. Kageshima and A. Fujiwara, “First-principles study on inversion layer properties of double-gate atomically thin silicon channels,” Applied Physics Letters, vol. 93, no. 4, Article ID 043516, 2008. View at Publisher · View at Google Scholar
  17. K. Nehari, N. Cavassilas, J. L. Autran, M. Bescond, D. Munteanu, and M. Lannoo, “Influence of band structure on electron ballistic transport in silicon nanowire MOSFET's: an atomistic study,” Solid-State Electronics, vol. 50, no. 4, pp. 716–721, 2006. View at Publisher · View at Google Scholar · View at Scopus
  18. P. V. Sushko and A. L. Shluger, “Electronic structure of insulator-confined ultra-thin Si channels,” Microelectronic Engineering, vol. 84, no. 9-10, pp. 2043–2046, 2007. View at Publisher · View at Google Scholar · View at Scopus
  19. M. De Michielis, D. Esseni, Y. L. Tsang et al., “A semianalytical description of the hole band structure in inversion layers for the physically based modeling of pMOS transistors,” IEEE Transactions on Electron Devices, vol. 54, no. 9, pp. 2164–2173, 2007. View at Publisher · View at Google Scholar · View at Scopus
  20. Y. Omura, “Extension of analytical model for conduction band nonparabolicity to transport analysis of nanoscale metal-oxide-semiconductor field-effect transistor,” Journal of Applied Physics, vol. 105, no. 1, Article ID 014310, 2009. View at Publisher · View at Google Scholar
  21. Y. Tamara and Y. Omura, “Empirical quantitative Modeling of threshold voltage of sub-50-nm double-gate SOI MOSFET’s,” Japanese Journal of Applied Physics, vol. 45, pp. 3074–3078, 2006. View at Publisher · View at Google Scholar · View at Scopus