Research Article
Novel Power Reduction Technique for ReRAM with Automatic Avoidance Circuit for Wasteful Overwrite
Table 2
Simulation condition.
| Simulator | HSPICE | Fabrication process | 180-nm CMOS | Power supply | 3.3 V | Temperature | 27°C | Amplification time | 70 ns | Bit-line capacitance (Cb) | 200 fF |
|
|