Design Optimization of Transistors Used for Neural Recording

Figure 7

Determination of the DC gate bias as a function of the moderate inversion transition. The blue line is the transconductance efficiency curve (left axis), and the black line is the drain (gate) voltage (right axis). Each of these are stepped a −0.250 V, 0 V and +0.250 V, voltage offset values. The selection of the knee in the transconductance efficiency curve leads to the selection of a 2 μA 𝐼_𝑑. The point at which this intersects the gate voltage to provide the DC gate voltage bias point. This pair of values is used to design the single-stage amplifier circuitry.