- About this Journal ·
- Abstracting and Indexing ·
- Aims and Scope ·
- Article Processing Charges ·
- Author Guidelines ·
- Bibliographic Information ·
- Citations to this Journal ·
- Contact Information ·
- Editorial Board ·
- Editorial Workflow ·
- Free eTOC Alerts ·
- Publication Ethics ·
- Recently Accepted Articles ·
- Reviewers Acknowledgment ·
- Submit a Manuscript ·
- Subscription Information ·
- Table of Contents
Active and Passive Electronic Components
Volume 2012 (2012), Article ID 565827, 9 pages
Analysis of Kink Reduction in SOI MOSFET Using Selective Back Oxide Structure
1Department of Electrical Engineering, American University of Sharjah, P.O. Box 26666, Sharjah, UAE
2Department of Electrical Engineering, Indian Institute of Technology, Kanpur 208016, India
3NERIST, Nirjuli, 791109, Itanagar, India
4Birla Institute of Technology, Mesra, 835 215 Ranchi, India
Received 1 March 2012; Accepted 9 May 2012
Academic Editor: Daisaburo Takashima
Copyright © 2012 M. Narayanan et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.
- J. B. Kuo and S. C. Lin, Low-Voltage SOI CMOS VLSI Devices and Circuits, John Wiley & Sons, 1st edition, 2001.
- A. marshall and S. Natarajan, SOI Design: Analog, Memory and Digital Techniques, Kluwer Academic Publishers, 2001.
- K. Bernstein and j. Norman, SOI Circuit Design Concepts, Kluwer Academic Publishers, 2000.
- J. Chen, R. Solomon, T. Y. Chan, P. K. Ko, and C. Hu, “Threshold voltage and C-V characteristics of SOI MOSFET's related to Si film thickness variation on SIMOX wafers,” IEEE Transactions on Electron Devices, vol. 39, no. 10, pp. 2346–2353, 1992.
- J. Z. Ren and C. A. T. Salama, “1 V SOI NMOSFET with suppressed floating body effects,” Solid-State Electronics, vol. 44, no. 11, pp. 1931–1937, 2000.
- B. A. Chen, A. Hirsch, S. K. Iyer, N. Rovedo, H. -J. Wann, and Y. Zhang, “Patterned Buried Insulator,” US Patent no. 6429091 B1, 2002.
- Y. Dong, M. Chen, J. Chen et al., “Patterned buried oxide layers under a single MOSFET to improve the device performance,” Semiconductor Science and Technology, vol. 19, no. 3, pp. L25–L28, 2004.
- C. Pal, B. Mazhari, and S. S. K. Iyer, “Simulation of MOSFET devices and circuits fabricated on selective buried oxide (SEL-BOX) substrates,” in Proceedings of IEEE Conference on Electron Devices and Solid-State Circuits (EDSSC '05), pp. 559–562, Hong Kong, December 2005.
- M. Y. Hammad, “Analytical modeling of the partially-depleted SOI MOSFET,” IEEE Transactions on Electron Devices, vol. 48, no. 2, pp. 252–258, 2001.
- ATHENA User's Manual Device Simulation Software, Silvaco International, Santa Clara, Calif, USA, 2004.
- ATLAS User's Manual Device Simulation Software, Silvaco International, Santa Clara, Calif, USA, 2004.
- J.-P. Colinge, Silicon-On-Insulator Technology: Materials to VLSI, Springer, 3rd edition, 2004.
- D. A. Neamen, Microelectronics, McGraw-Hill, 3rd edition, 2006.
- I. M. Hafez, G. Ghibaudo, and F. Balestra, “Analysis of the kink effect in MOS transistors,” IEEE Transactions on Electron Devices, vol. 37, no. 3, pp. 818–821, 1990.
- T. Y. Chan and P. K. Ko, “A simple method to characterize substrate current in MOSFET's,” IEEE Electron Device Letters, vol. EDL-5, no. 12, p. 506, 1984.