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Active and Passive Electronic Components
Volume 2012 (2012), Article ID 763572, 10 pages
http://dx.doi.org/10.1155/2012/763572
Research Article

Thermal-Aware Test Schedule and TAM Co-Optimization for Three-Dimensional IC

1Department of Electrical Engineering, National Taiwan University, Taipei 10617, Taiwan
2Department of Electrical Engineering, Tamkang University, New Taipei City 25137, Taiwan
3Department of Electrical and Computer Engineering, Duke University, Durham, NC 27708, USA

Received 27 April 2012; Revised 7 October 2012; Accepted 18 October 2012

Academic Editor: Gerard Ghibaudo

Copyright © 2012 Chi-Jih Shih et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Abstract

Testing is regarded as one of the most difficult challenges for three-dimensional integrated circuits (3D ICs). In this paper, we want to optimize the cost of TAM (test access mechanism) and the test time for 3D IC. We used both greedy and simulated annealing algorithms to solve this optimization problem. We compare the results of two assumptions: soft-die mode and hard-die mode. The former assumes that the DfT of dies cannot be changed, while the latter assumes that the DfT of dies can be adjusted. The results show that thermal-aware cooptimization is essential to decide the optimal TAM and test schedule. Blindly adding TAM cannot reduce the total test cost due to temperature constraints. Another conclusion is that soft-die mode is more effective than hard-die mode to reduce the total test cost for 3D IC.