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Active and Passive Electronic Components
Volume 2012 (2012), Article ID 763572, 10 pages
Thermal-Aware Test Schedule and TAM Co-Optimization for Three-Dimensional IC
1Department of Electrical Engineering, National Taiwan University, Taipei 10617, Taiwan
2Department of Electrical Engineering, Tamkang University, New Taipei City 25137, Taiwan
3Department of Electrical and Computer Engineering, Duke University, Durham, NC 27708, USA
Received 27 April 2012; Revised 7 October 2012; Accepted 18 October 2012
Academic Editor: Gerard Ghibaudo
Copyright © 2012 Chi-Jih Shih et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.
- W. R. Davis, J. Wilson, S. Mick et al., “Demystifying 3D ICs: the pros and cons of going vertical,” IEEE Design and Test of Computers, vol. 22, no. 6, pp. 498–510, 2005.
- E. J. Marinissen and Y. Zorian, “Testing 3D chips containing through-silicon vias,” in Proceedings of the International Test Conference (ITC '09), paper ET1.1, November 2009.
- R. S. Patti, “Three-dimensional integrated circuits and the future of system-on-chip designs,” Proceedings of the IEEE, vol. 94, no. 6, pp. 1214–1224, 2006.
- S. Das, A. Chandrakasan, and R. Reif, “Timing, energy, and thermal performance of three-dimensional integrated circuits,” in Proceedings of the ACM Great lakes Symposium on VLSI (GLSVLSI '04), pp. 338–343, April 2004.
- S. Im and K. Banerjee, “Full chip thermal analysis of planar (2-D) and vertically integrated (3-D) high performance ICs,” in Proceedings of IEEE International Electron Devices Meeting (IEDM '00), pp. 727–730, December 2000.
- K. Puttaswamy and G. H. Loh, “Thermal analysis of a 3D die-stacked high-performance microprocessor,” in Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI '06), pp. 19–24, May 2006.
- C. Sun, L. Shang, and R. P. Dick, “Three-dimensional multiprocessor system-on-chip thermal optimization,” in Proceedings of the 5th International Conference on Hardware/Software Codesign and System Synthesis, pp. 117–122, October 2007.
- K. Chakrabarty, “Test scheduling for core-based systems using mixed-integer linear programming,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 19, no. 10, pp. 1163–1174, 2000.
- V. Iyengar and K. Chakrabarty, “Precedence-based, preemptive, and power-constrained test scheduling for system-on-a-chip,” in Proceedings of the 19th IEEE VLSI Test Symposium (VTS' 01), pp. 368–374, May 2001.
- C. Liu, K. Veeraraghavan, and V. Iyengar, “Thermal-aware test scheduling and hot spot temperature minimization for core-based systems,” in Proceedings of the 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT '05), pp. 552–560, October 2005.
- T. E. Yu, T. Yoneda, K. Chakrabarty, and H. Fujiwara, “Thermal-safe test access mechanism and wrapper co-optimization for system-on-chip,” in Proceedings of the 16th Asian Test Symposium (ATS '07), pp. 187–192, October 2007.
- P. Rosinger, B. M. Al-Hashimi, and K. Chakrabarty, “Thermal-safe test scheduling for core-based system-on-chip integrated circuits,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 25, no. 11, pp. 2502–2511, 2006.
- C. Yao, K. K. Saluja, and P. Ramanathan, “Power and thermal constrained test scheduling under deep submicron technologies,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 30, no. 2, pp. 317–322, 2011.
- B. Noia, K. Chakrabarty, and E. J. Marinissen, “Optimization methods for post-bond die-internal/external testing in 3D stacked ICs,” in Proceedings of the 41st International Test Conference (ITC '10), pp. 1–10, November 2010.
- K. Skadron, M. R. Stan, K. Sankaranarayanan, W. Huang, S. Velusamy, and D. Tarjan, “Temperature-aware microarchitecture: modeling and implementation,” ACM Transaction on Architecture and Code Optimization, vol. 1, no. 1, pp. 94–125, 2004.
- P. Girard, “Survey of low-power testing of VLSI circuits,” IEEE Design and Test of Computers, vol. 19, no. 3, pp. 82–92, 2002.
- E. J. Marinissen, J. Verbree, and M. Konijnenburg, “A structured and scalable test access architecture for TSV-based 3D stacked ICs,” in Proceedings of the 28th IEEE VLSI Test Symposium (VTS '10), pp. 269–274, April 2010.
- M. Taouli, S. Hamdioui, K. Beenakker, and E. J. Marinissen, “Test impact on the overall die-to-wafer 3D stacked IC cost,” Journal of Electronic Testing, vol. 28, pp. 15–25, 2011.
- Y. R. Huang, J. H. Pan, and Y. C. Lu, “Thermal-aware router-sharing architecture for 3D network-on-chip designs,” in Proceedings of the Asia Pacific Conference on Circuit and System (APCCAS '10), pp. 1087–1090, December 2010.
- E. J. Marinissen, V. Iyengar, and K. Chakrabarty, “ITC’02 SoC Test Benchmarks,” http://www.extra.research.philips.com/itc02socbenchm.