Table 1: The first test case.

DieCircuitTechnology
(nm)
Die power (W)No. of coresNo. of scan chainNo. of test patternTAM width
(hard-die mode)
Test time (No. of test cycles)

Die 4Logic18036.09151301776,440
Die 3Logic18036.09151301776,440
Die 2ARM91806.022030022210,000
Die 1SRAM900.6525N/AN/A2425,984
Die 0DRAM320.31N/AN/A2500,000