Table 2: Comparison of effects of different techniques in SRAM designing.

CriteriaReferences
[4][16][17][18][19][15][9]

TechniqueStacking and length sizing, power gating in standby, and compressionBuffered read, and reconfigurable UDVS supportBuffered read, control of supply, buffered voltages and SASingle-ended, 2% bit redundancy, body, header and footer biasSegmented virtual groundingColumn-wise write, DCVSL read controlSchmitt trigger based
Main noveltyUsing ROM and new cell designReconfigurabilityRedundancy in SAsNew cell designSuper-threshold readSoft-error addressingUsing ST design
Technology0.18 μm65 nm65 nm0.13 μm0.13 μm90 nm0.13 μm
Size (bits)6464 K256 K2 K40 K32 K & 49 K4 K
Frequency (KHz)~35 at 450 mV
121 at 500 mV
200,000 at 1.2 V
500 at 250 mV
25 at 350 mV205 at 300 mV
21.5 at 210 mV
100,000 at 400 mV581.4 at 300 mV
0.5 at 160 mV
620 at 400 mV
Area overhead910% to 6 TNot reported30% to 6 T42% to 6 T [20]8% to 6 T61% to 8 T ~200% to 6 T
Total leakage/size (pA)Not reported~700 at 1.2 V
~30.5 at 250 mV
~24 at 350 mV
~21 at 300 mV
~122 at 300 mV27 at 400 mV~24.11 at 300 mV~90 at 400 mV
Energy/access/size (fJ)~0.000058 at 500 mV0.167 at 400 mV~0.396 at 350 mV0.488 at 340 mV
0.38 at 300 mV
0.17 at 400 mV0.056 at 300 mV
(Write)
0.094 at 300 mV (Read)
50% and 18% lower dynamic and leakage power to 6 T at 175 mV
Min voltage (mV)450250350193360160160
transistors14 T8 T8 T6 T6 T10 T10 T
Bit error rateNot reportedRead static noise margin (SNM) eliminatedRead SNM eliminated2% at 120 mV3.5% at 330 mV60.3 mV mean Read and ~91 mV mean Hold SNM at 300 mV~56.5 mV mean Read and ~118 mV mean Hold SNM at 400 mV [21]
Min energy voltage (mV)450400350340Not reported160160
ProsLow energyHigh performanceLow read error rateVariability aware designVery high performanceLow energy, high read SNMLow voltage, high read SNM
ConsLarge area overhead, SNM not discussedPVT variations not discussedLow frequencyStill high leakage currentNot DVS enabledLeakage increase at typical tempLarge area overhead