Table 3: Comparison of pipelining strategies.

CriteriaReferences
[27][28][29][30][31]

TechniqueInstruction isolationDVFS and critical path isolation under temperature variationsVariable clock in times of process variationsSoft edge flip-flopFlow-through latch between stages and selection of different voltages
Technology45 nmBPTM 70 nm90 nmPTM 65 nmPTM 32 nm
Circuit32-bit in-order 5-stage dual-pipeline processor with IA32in-order superscalar pipeline with the Alpha ISA32-bit microprocessor34-bit pipelined adder6 stages pipelined FPU
Frequency1.25 GHz1.5–3 GHz~0.1–1 GHz2–2.5 GHzImproves BIPS/W by 47% (actual frequency not reported)
Area and/or frequency impact28% performance reduction due to instruction isolation~4.5% area overhead /3.4–11% frequency overhead2.6% area overhead/13%–50% performance improvement5–20% performance improvement40% performance improvement
Energy/Temperature impact13% power reductionReduces temperature by 6.6–9%3% energy overhead19% power saving (4.9 mW)Not reported
Min voltage740 mV for ADD 680 mV for XOR and AND700 mVScaling from 1.2 V to 1 VScaling from 1.2 V to 1.05 V (5–20% 𝑉 D D reduction)Scaling from 1.4 V to 0.95 V
ProsDVS enabledTemperature variations tolerant, DVFS enabledLow energy and area overheadRather large power reductionRather large performance improvement
ConsPerformance reductionPV variations not discussedNot supporting very low voltagesNot supporting very low voltages, PVT variations not discussedNot supporting very low voltages