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Active and Passive Electronic Components

Volume 2013 (2013), Article ID 153157, 9 pages

http://dx.doi.org/10.1155/2013/153157

## Potential and Quantum Threshold Voltage Modeling of Gate-All-Around Nanowire MOSFETs

^{1}Pandian Saraswathi Yadav Engineering College, Sivagangai, India^{2}Thiagarajar Engineering College, Madurai, India^{3}St. Michael’s College of Engineering and Technology, Sivagangai, India

Received 21 March 2013; Revised 15 August 2013; Accepted 15 August 2013

Academic Editor: Gerard Ghibaudo

Copyright © 2013 M. Karthigai Pandian et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

#### Abstract

An improved physics-based compact model for a symmetrically biased gate-all-around (GAA) silicon nanowire transistor is proposed. Short channel effects and quantum mechanical effects caused by the ultrathin silicon devices are considered in modelling the threshold voltage. Device geometrics play a very important role in multigate devices, and hence their impact on the threshold voltage is also analyzed by varying the height and width of silicon channel. The inversion charge and electrical potential distribution along the channel are expressed in their closed forms. The proposed model shows excellent accuracy with TCAD simulations of the device in the weak inversion regime.

#### 1. Introduction

Semiconductor nanowires are attractive components for future nanoelectronics since they can exhibit a wide range of device function and at the same time serve as bridging wires that connect larger scale metallization. The nanoscale FETs based on silicon nanowires have notable attention for their potential applications in electronics industry. In a continuous effort to increase current drive and better control over SCEs, silicon-on-insulator (SOI) MOS transistors have evolved from classical, planar, and single-gate devices into 3D devices with a multigate structure (double-, triple-, or gate-all-around devices). These multigate nanowire FETs that prevent the electric field lines from originating at the drain from terminating under the channel region are now widely recognized as one of the most auspicious solutions, for meeting the roadmap requirements in the decananometer scale. Multigate device structures of nanowire transistors pave the way for better electrostatic control, and as a result, intrinsic channels get higher mobility and current [1].

CMOS devices can be scaled down up to a channel length of 10 nm when the number of gates in the device is increased. In such transistors the short channel effects are controlled by the device geometry, and hence an undoped or lightly doped ultrathin body is used to sustain the channel. Various device structures such as double gate fully depleted SOI, trigate, and all around gate structures have been extensively investigated to restrict SCEs within a limit while achieving the primary advantages of scaling, that is, higher performance, lower power, and ever increasing integration density [2]. The scaling theory and the analytical SCEs model for nanowire transistors based on the concept of natural length are successful to a certain extent. To address the issue of 2D effects in the gate insulator, a more generalized concept of scale length has been proposed recently [3, 4].

Modeling of quantum confinement and transport in a nanowire transistor has been addressed in the literature [5–7]. The undoped cylindrical body GAA field effect transistor, that has a great control over the corner effects and channel, is considered to be promising candidate for sub-45 nm regime [8, 9]. An analytical threshold voltage model for GAA nanoscale MOSFETs (Figure 1) considering the hot carrier induced interface charges has been proposed by Ghoggali et al., in 2008 [10]. Quantum confinement and its effect on threshold voltage variations in short channel GAA devices have been studied in 2009 [11]. A compact analytical threshold voltage model proposed by Te-Kuang deals with the interface trapped charges in a nanowire channel [12]. A physically based classical model for body potential of a cylindrical GAA nanowire transistor has been proposed by Ray and Mahapatra in 2008 [13], and a quasianalytical model for predicting the potential of a nanowire FET has been proposed by De Michielis et al., in 2010 [14].

In this paper quantum threshold voltage modeling of a lightly doped gate-all-around silicon nanowire transistor is proposed. In modeling the threshold voltage, the quantum effects are also taken into account, as the quantization of electron energy in ultrathin devices can never be ignored. One important consequence of the quantum mechanical carrier distribution, in accordance with the device behavior, occurs when the device geometrics and the silicon thickness are varied, so a reliable compact model for the nanowire transistors must also take into account quantum effects resulting out of these variations. The proposed physically based closed form quantum threshold voltage model holds good for ultrathin and ultrashort channel gate all around devices and does not discuss any unphysical fitting parameter. The compact threshold voltage model is obtained by solving the 3D Poisson equation and 2D Schrodinger equations in the weak inversion region. These equations are then consistently solved to obtain the potential distribution and inversion charge density.

#### 2. Threshold Voltage Modeling

Here, we consider a lightly doped nanowire MOSFET in the weak inversion region, where both fixed and mobile charge densities in the channel are negligible. We have assumed a flat potential on the plane perpendicular to the source-drain direction. Poisson-Schrödinger equations should be solved consistently to obtain the potential and inversion charge density. But, in the weak inversion regime, we have approximated the Poisson equation as Laplace equation with the inversion charge density neglected, and thus the two equations are decoupled. The midgap metals are used for gate, intended to suppress the silicon gate poly depletion induced parasitic capacitances [15]. The 3D Poisson equation is solved to obtain the threshold voltage in the weak inversion region, including the parabolic band approximation. The potential distribution in insulator and silicon regions can be expressed as

The potential in terms of (width), (height), and (length) is to be determined. The boundary conditions defined by the physics of the device are given by For a gate-all-around device, we have to find the insulator potential on all sides of the channel under consideration. So the height and width of the channel are also taken into account. The insulator potential is now expressed as where is the gate voltage, is the built-in potential, is the channel length, and is the drain to source voltage which is negligible for low . is the work function difference. By applying the superposition principle, the electrostatic potential can be now written as Here is the 1D solution of the Poisson equation that satisfies the gate boundary conditions. satisfies the source boundary condition, but it is bound to have a null value on the gate and drain boundaries. Similarly satisfies the drain boundary condition, and it is bound to have a null value on the gate and source boundaries. On further evaluation, the term is found to satisfy the potential equation when is on null value, and in an exact repetition, the term satisfies the potential equation when is on null value. From (1), By solving the above equation using LDE method, we obtain the value of . Then the limits are applied on the equation using the boundary conditions. Now the potentials is given by

Similarly the values of potential are also derived as follows: where and , , , , , and are constants. From (6) and (8), and are found to be continuous in the direction (). The first derivative function itself has times discontinuities at the silicon insulator interfaces. Thus, applying continuity in both equations, we proceed to equate (6) and (8) as follows: Differentiating (6) with respect to , Differentiating (8) with respect to , Equating (11) and (12), Dividing (10) by (13), Likewise, from (7) and (8), and are found to be continuous in the direction . The function itself has discontinuities at the silicon insulator interfaces which are proportional to the dielectric constant . Thus, applying continuity in both equations and equating (7) and (8), we get Differentiating (7) with respect to , Differentiating (8) with respect to , Equating (16) and (17), Dividing (15) by (18), This natural length is an easy guide for choosing device parameters and has simple physical meaning that a small natural length corresponds to superb short channel effect immunity [4]. The value of and depends on device parameters. The potential can be modified as Similarly, the potential can be modified as Now the can be obtained from the potential equations (20) by using different multipliers in different regions: Subsequently the constants , , and are evaluated suitably: From (20), the potential can be rewritten as By multiplying with the corresponding orthogonal conjugate functions and integrating, coefficients of can be obtained. The coefficients of are also obtained in a similar method: The above integrals (25) are evaluated to obtain explicit expressions for and as follows: where And the values of and are given by The potential equation is now rewritten as where Once the potential distribution at every point of the cross-section of the channel is known, we calculate the inversion charge density by using surface integral over the surface area of the channel. When the integrated charge at virtual source becomes equal to critical charge, the gate voltage of a lightly doped body device is nearly equal to the threshold voltage of the device. Hence the inversion charge can be expressed as where is the elementary charge, is thermal voltage, and is the intrinsic carrier concentration.

The charge equation can now be approximated as Here, is the virtual source position, which is half of the channel length for low . Using the inversion charge we can obtain the classical threshold model as expressed in the following:

#### 3. Quantum Threshold Voltage Modeling

As MOSFET devices are further scaled into the deep nanometer regime, it has become necessary to include quantum mechanical effects while modeling their device behavior. In this paper, we approximate the actual potential well as the square well potential since it is difficult to solve the Schrödinger equation to obtain the potential expressed in (29). The square well potential of a gate-all-around nanowire transistor is shown in Figure 2. The quantum charge of the device is expressed as where is the 1D density-of-states and is the Fermi-Dirac distribution function. is the energy of the electron wave. The terms and are positive natural numbers.

In silicon, six energy valleys are found to be present in its band structure (two lower energy valleys, two middle energy valleys, and two higher energy valleys). If the thin film of device has equal height and width, the two lower energy valleys and two middle energy valleys are combined together to produce four lower energy valleys, and the other two higher energy valleys remain in their own state. Thus, the charge is given by where is the mass of the valley which is perpendicular to the direction of quantization. The Fermi energy level is much lower than the conduction band energy in weak inversion region. Hence the charge equation can be approximated as Using the Schrödinger equation, the value of is determined by the following formulation [5]: where the conduction band energy is given as Using (36) and (37), the integrated charge can be obtained as where Here the and are the transverse and longitudinal effective masses of the energy valleys of silicon. The lengths and carry distinct values contingent on the direction of quantization. Finally, the quantum threshold voltage model becomes where The impacts on the threshold voltage due to quantum effects are acquired by using the following equation: Here, is the difference between the quantum threshold voltage and the classical threshold voltage.

#### 4. Results and Discussion

Figure 3 shows the electrostatic potential of the proposed gate all around transistor, and it is found to be constant value at 0.3 V. Continuously varying the and terms in (4) has no impact on the potential as it remains constant along the insulator boundaries. This is totally in contrast to the results obtained in [15] where the potential is found to be linearly varying in the insulator boundaries. The constant potential has to be deduced as the resultant of the gate voltage applied symmetrically across the four sides of the transistor. The TCAD simulation of the device shows that the electrostatic potential is constant at 0.296 V. The simulation results are found to in acceptance with the TCAD results.

Figure 4 represents the variation of total quantum integrated charge with the gate voltage. Equation (39) is used to obtain the integrated charge with only one energy level and one series term. It clearly shows that the decrease in the film thickness leads to the increase in the quantum threshold voltage which is actually due to the increase in energy quantization of the transistor. With the height and length of the device being constant, the width of the device is varied, and henceforth the variation of charge in accordance with the gate voltage is illustrated in Figure 4.

The variation of quantum threshold voltage with width and height of the film at a channel length of 20 nm is shown in Figure 5. The short channel effects tend to decrease along with the energy quantisation, and this can be further explained as a result of increase in the effective band gap of silicon due to quantum effects. The effect of confinement, expressed as the difference in the threshold voltage and its variation with the channel length , is illustrated in Figure 6. The most important thing about this gate all around nanowire transistor is that any change in one of the dimensions can be nullified by proper tuning of other dimensions as the transistor is symmetric about its height and width.

Figure 7 shows the variation of the classical threshold voltage and quantum threshold voltage with the film height at a constant width of 9 nm. The value of the classical threshold voltage ranges from 0.27 V to 0.29 V for the corresponding changes in the film height. Similarly the quantum threshold voltage ranges from 0.3 V to 0.31 V. It shows that the device has a highly improved control over the threshold voltage. The TCAD results justify the simulation results.

#### 5. Conclusion

In this paper, a quantum threshold voltage model for a GAA silicon nanowire transistor is proposed by solving the 3D Poisson and Schrodinger equations. Analytical expressions for potential and the inversion charge are expressed in their closed forms. The results show that the integrated charge and the threshold voltage calculated in accordance with the quantum effects of this proposed model are highly improved. The future considerations include deriving the I-V characteristics of the gate all around nanowire transistors and studying the impact of scaling on various device parameters. Finally, to conclude, this model provides an analytical and useful way for the threshold voltage evaluations in gate all around nanowire devices with a unified formalism employed in both classical and quantum mechanical approaches.

#### References

- J. Wang, E. Polizzi, and M. Lundstrom, “A computational study of ballistic silicon nanowire transistors,” in
*Proceedings of the IEEE International Electron Devices Meeting*, pp. 695–698, December 2003. View at Scopus - J. P. Colinge,
*FINFETS and Other Multi-Gate Transistors*, Springer, New York, NY, USA, 2007. - D. J. Frank, Y. Taur, and H.-S. P. Wong, “Generalized scale length for two-dimensional effects in MOSFET's,”
*IEEE Electron Device Letters*, vol. 19, no. 10, pp. 385–387, 1998. View at Publisher · View at Google Scholar · View at Scopus - B. Yu, L. Wang, Y. Yuan, P. M. Asbeck, and Y. Taur, “Scaling of nanowire transistors,”
*IEEE Transactions on Electron Devices*, vol. 55, no. 11, pp. 2846–2858, 2008. View at Publisher · View at Google Scholar · View at Scopus - G. D. Sanders, C. J. Stanton, and Y. C. Chang, “Theory of transport in silicon quantum wires,”
*Physical Review B*, vol. 48, no. 15, pp. 11067–11076, 1993. View at Publisher · View at Google Scholar · View at Scopus - M.-Y. Shen and S.-L. Zhang, “Band gap of a silicon quantum wire,”
*Physics Letters A*, vol. 176, no. 3-4, pp. 254–258, 1993. View at Scopus - J. P. Colinge, X. Baie, V. Bayot, and E. Grivei, “Quantum-wire effects in thin and narrow SOI MOSFETs,” in
*Proceedings of the IEEE International SOI Conference*, pp. 66–67, October 1995. View at Scopus - C. P. Auth and J. D. Plummer, “Scaling theory for cylindrical, fully-depleted, surrounding-gate MOSFET's,”
*IEEE Electron Device Letters*, vol. 18, no. 2, pp. 74–76, 1997. View at Publisher · View at Google Scholar · View at Scopus - J.-T. Park and J.-P. Colinge, “Multiple-gate SOI MOSFETs: device design guidelines,”
*IEEE Transactions on Electron Devices*, vol. 49, no. 12, pp. 2222–2229, 2002. View at Publisher · View at Google Scholar · View at Scopus - Z. Ghoggali, F. Djeffal, M. A. Abdi, D. Arar, N. NLakhdar, and T. TBendib, “An analytical threshold voltage model for nanoscale,” in
*Proceedings of the 3rd International Design and Test Workshop (IDT '08)*, pp. 93–97, December 2008. View at Publisher · View at Google Scholar · View at Scopus - Y.-S. Wu and P. Su, “Quantum confinement effect in short-channel gate-all-around MOSFETs and its impact on the sensitivity of threshold voltage to process variations,” in
*Proceedings of the IEEE International SOI Conference*, October 2009. View at Publisher · View at Google Scholar · View at Scopus - C. Te-Kuang, “A compact analytical threshold-voltage model for surrounding-gate MOSFETs with interface trapped charges,”
*IEEE Electron Device Letters*, vol. 31, no. 8, pp. 788–790, 2010. View at Publisher · View at Google Scholar · View at Scopus - B. Ray and S. Mahapatra, “Modeling and analysis of body potential of cylindrical gate-all-around nanowire transistor,”
*IEEE Transactions on Electron Devices*, vol. 55, no. 9, pp. 2409–2416, 2008. View at Publisher · View at Google Scholar · View at Scopus - L. De Michielis, L. Selmi, and A. M. Ionescu, “A quasi-analytical model for nanowire FETs with arbitrary polygonal cross section,”
*Solid-State Electronics*, vol. 54, no. 9, pp. 929–934, 2010. View at Publisher · View at Google Scholar · View at Scopus - P. R. Kumar and S. Mahapatra, “Quantum threshold voltage modeling of short channel quad gate silicon nanowire transistor,”
*IEEE Transactions on Nanotechnology*, vol. 10, no. 1, pp. 121–128, 2011. View at Publisher · View at Google Scholar · View at Scopus