About this Journal Submit a Manuscript Table of Contents
Active and Passive Electronic Components
Volume 2013 (2013), Article ID 153157, 9 pages
http://dx.doi.org/10.1155/2013/153157
Research Article

Potential and Quantum Threshold Voltage Modeling of Gate-All-Around Nanowire MOSFETs

1Pandian Saraswathi Yadav Engineering College, Sivagangai, India
2Thiagarajar Engineering College, Madurai, India
3St. Michael’s College of Engineering and Technology, Sivagangai, India

Received 21 March 2013; Revised 15 August 2013; Accepted 15 August 2013

Academic Editor: Gerard Ghibaudo

Copyright © 2013 M. Karthigai Pandian et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Linked References

  1. J. Wang, E. Polizzi, and M. Lundstrom, “A computational study of ballistic silicon nanowire transistors,” in Proceedings of the IEEE International Electron Devices Meeting, pp. 695–698, December 2003. View at Scopus
  2. J. P. Colinge, FINFETS and Other Multi-Gate Transistors, Springer, New York, NY, USA, 2007.
  3. D. J. Frank, Y. Taur, and H.-S. P. Wong, “Generalized scale length for two-dimensional effects in MOSFET's,” IEEE Electron Device Letters, vol. 19, no. 10, pp. 385–387, 1998. View at Publisher · View at Google Scholar · View at Scopus
  4. B. Yu, L. Wang, Y. Yuan, P. M. Asbeck, and Y. Taur, “Scaling of nanowire transistors,” IEEE Transactions on Electron Devices, vol. 55, no. 11, pp. 2846–2858, 2008. View at Publisher · View at Google Scholar · View at Scopus
  5. G. D. Sanders, C. J. Stanton, and Y. C. Chang, “Theory of transport in silicon quantum wires,” Physical Review B, vol. 48, no. 15, pp. 11067–11076, 1993. View at Publisher · View at Google Scholar · View at Scopus
  6. M.-Y. Shen and S.-L. Zhang, “Band gap of a silicon quantum wire,” Physics Letters A, vol. 176, no. 3-4, pp. 254–258, 1993. View at Scopus
  7. J. P. Colinge, X. Baie, V. Bayot, and E. Grivei, “Quantum-wire effects in thin and narrow SOI MOSFETs,” in Proceedings of the IEEE International SOI Conference, pp. 66–67, October 1995. View at Scopus
  8. C. P. Auth and J. D. Plummer, “Scaling theory for cylindrical, fully-depleted, surrounding-gate MOSFET's,” IEEE Electron Device Letters, vol. 18, no. 2, pp. 74–76, 1997. View at Publisher · View at Google Scholar · View at Scopus
  9. J.-T. Park and J.-P. Colinge, “Multiple-gate SOI MOSFETs: device design guidelines,” IEEE Transactions on Electron Devices, vol. 49, no. 12, pp. 2222–2229, 2002. View at Publisher · View at Google Scholar · View at Scopus
  10. Z. Ghoggali, F. Djeffal, M. A. Abdi, D. Arar, N. NLakhdar, and T. TBendib, “An analytical threshold voltage model for nanoscale,” in Proceedings of the 3rd International Design and Test Workshop (IDT '08), pp. 93–97, December 2008. View at Publisher · View at Google Scholar · View at Scopus
  11. Y.-S. Wu and P. Su, “Quantum confinement effect in short-channel gate-all-around MOSFETs and its impact on the sensitivity of threshold voltage to process variations,” in Proceedings of the IEEE International SOI Conference, October 2009. View at Publisher · View at Google Scholar · View at Scopus
  12. C. Te-Kuang, “A compact analytical threshold-voltage model for surrounding-gate MOSFETs with interface trapped charges,” IEEE Electron Device Letters, vol. 31, no. 8, pp. 788–790, 2010. View at Publisher · View at Google Scholar · View at Scopus
  13. B. Ray and S. Mahapatra, “Modeling and analysis of body potential of cylindrical gate-all-around nanowire transistor,” IEEE Transactions on Electron Devices, vol. 55, no. 9, pp. 2409–2416, 2008. View at Publisher · View at Google Scholar · View at Scopus
  14. L. De Michielis, L. Selmi, and A. M. Ionescu, “A quasi-analytical model for nanowire FETs with arbitrary polygonal cross section,” Solid-State Electronics, vol. 54, no. 9, pp. 929–934, 2010. View at Publisher · View at Google Scholar · View at Scopus
  15. P. R. Kumar and S. Mahapatra, “Quantum threshold voltage modeling of short channel quad gate silicon nanowire transistor,” IEEE Transactions on Nanotechnology, vol. 10, no. 1, pp. 121–128, 2011. View at Publisher · View at Google Scholar · View at Scopus