MCML D-Latch Using Triple-Tail Cells: Analysis and Design

Figure 5

Simulated and predicted delay of proposed D-latch versus 𝐼_SS with NM = 130 mV, 𝐴_𝑣=4, and different load capacitances (a) 𝐶_𝐿=0 fF, (b) 𝐶_𝐿=10 fF, (c) 𝐶_𝐿=100 fF, and (d) 𝐶_𝐿=1 pF.

(a)

(b)

(c)

(d)