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Active and Passive Electronic Components
Volume 2013 (2013), Article ID 217674, 9 pages
MCML D-Latch Using Triple-Tail Cells: Analysis and Design
1Electronics and Communication Division, Delhi Technological University, Delhi 110042, India
2Electronics and Communication Division, Netaji Subhas Institute of Technology, Delhi 110078, India
Received 25 June 2013; Accepted 17 September 2013
Academic Editor: Ching Liang Dai
Copyright © 2013 Kirti Gupta et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.
- S. Kiaei and D. Allstot, “Low-noise logic for mixed-mode VLSI circuits,” Microelectronics Journal, vol. 23, no. 2, pp. 103–114, 1992.
- M. Anis, M. Allam, and M. Elmasry, “Impact of technology scaling on CMOS logic styles,” IEEE Transactions on Circuits and Systems II, vol. 49, no. 8, pp. 577–589, 2002.
- M. Alioto and G. Palumbo, “Design strategies for source coupled logic,” IEEE Transactions on Circuits and Systems I, vol. 50, no. 5, pp. 640–654, 2003.
- N. H. E. Weste, D. Harris, and A. Banerjee, CMOS VLSI Design: A Circuits and System Perspective, Pearson Education, New York, NY, USA, 4th edition, 2010.
- J. Kundan and S. M. Hasan, “Enhanced folded source-coupled logic technique for low-voltage mixed-signal integrated circuits,” IEEE Transactions on Circuits and Systems II, vol. 47, no. 8, pp. 810–817, 2000.
- J. M. Musicer and J. Rabaey, “MOS current mode logic for low power, low noise CORDIC computation in mixed-signal environments,” in Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED '00), pp. 102–107, July 2000.
- S. Bruma, “Impact of on-chip process variations on MCML performance,” in Proceedings of the IEEE International Systems-on-Chip Conference, pp. 135–140, September 2003.
- H. Hassan, M. Anis, and M. Elmasry, “MOS current mode circuits: analysis, design, and variability,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 13, no. 8, pp. 885–898, 2005.
- M. Alioto and G. Palumbo, Model and Design of Bipolar and MOS Current-Mode Logic (CML, ECL and SCL Digital Circuits), Springer, New York, NY, USA, 2005.
- G. Caruso and A. Macchiarella, “A methodology for the design of MOS current-mode logic circuits,” IEICE Transactions on Electronics, vol. 93, no. 2, pp. 172–181, 2010.
- M. Alioto and G. Palumbo, “Power-aware design of nanometer MCML tapered buffers,” IEEE Transactions on Circuits and Systems II, vol. 55, no. 1, pp. 16–20, 2008.
- G. Caruso, “Power-aware design of MCML logarithmic adders,” in Proceedings of the International Conference on Signals and Electronic Systems (ICSES '10), pp. 281–283, September 2010.
- Y. M. El-Hariry and A. H. Madian, “MOS current mode logic realization of digital arithmetic circuits,” in Proceedings of the International Conference on Microelectronics (ICM '10), pp. 128–131, Cairo, Egypt, December 2010.
- O. Musa and M. Shams, “An efficient delay model for MOS current-mode logic automated design and optimization,” IEEE Transactions on Circuits and Systems I, vol. 57, no. 8, pp. 2041–2052, 2010.
- A. Cevrero, F. Regazzoni, M. Schwander, S. Badel, P. Ienne, and Y. Leblebici, “Power-gated MOS current mode logic (PG-MCML): a power aware DPA-resistant standard cell library,” in Proceedings of the 48th ACM/EDAC/IEEE Design Automation Conference (DAC '11), pp. 1014–1019, San Diego, Calif, USA, June 2011.
- M. Alioto, R. Mita, and G. Palumbo, “Design of high-speed power-efficient MOS current-mode logic frequency dividers,” IEEE Transactions on Circuits and Systems II, vol. 53, no. 11, pp. 1165–1169, 2006.
- R. Nonis, E. Palumbo, P. Palestri, and L. Selmi, “A design methodology for MOS current-mode logic frequency dividers,” IEEE Transactions on Circuits and Systems II, vol. 54, no. 2, pp. 245–254, 2007.
- J. K. Shin, T. W. Yoo, and M. S. Lee, “Design of half-rate linear phase detector using MOS current-mode logic gates for 10-Gb/s clock and data recovery circuit,” in Proceedings of the 7th International Conference on Advanced Communication Technology (ICACT '05), pp. 205–212, February 2005.
- C. Zhou, L. Zhang, H. Wang et al., “A 1 mW power-efficient high frequency CML 2:1 divider,” Analog Integrated Circuits and Signal Processing, vol. 71, no. 3, pp. 515–523, 2012.
- S. B. Anand and B. Razavi, “A CMOS clock recovery circuit for 2.5-Gb/s NRZ data,” IEEE Journal of Solid-State Circuits, vol. 36, no. 3, pp. 432–439, 2001.
- K. Gupta, N. Pandey, and M. Gupta, “Low-voltage MOS current mode logic multiplexer,” Radioengineering Journal, vol. 22, pp. 259–268, 2013.
- K. Gupta, N. Pandey, and M. Gupta, “Analysis and design of MOS current mode logic exclusive-OR gate using triple-tail cells,” Microelectronics Journal, vol. 44, no. 6, pp. 561–567, 2013.
- M. Alioto, R. Mita, and G. Palumbo, “Performance evaluation of the low-voltage CML D-latch topology,” Integration, vol. 36, no. 4, pp. 191–209, 2003.
- M. Alioto and G. Palumbo, “Power-delay optimization of D-latch/MUX source coupled logic gates,” International Journal of Circuit Theory and Applications, vol. 33, no. 1, pp. 65–86, 2005.
- H. Hassan, M. Anis, and M. Elmasry, “Low-power multi-threshold MCML: analysis, design, and variability,” Microelectronics Journal, vol. 37, no. 10, pp. 1097–1104, 2006.
- M. Alioto, G. Palumbo, and S. Pennisi, “Modelling of source-coupled logic gates,” International Journal of Circuit Theory and Applications, vol. 30, no. 4, pp. 459–477, 2002.
- J. Rabaey, Digital Integrated Circuits: A Design Perspective, Prentice-Hall, Englewood Cliffs, NJ, USA, 4th edition, 2009.