Table 2: Effect of process variation on static parameters of the proposed and the traditional D-latch.

ParameterNMOS
TFSFS
PMOS
TFSSF

(mV)
 Proposed427590327447417
 Traditional416508300509457
 Proposed4.35.343.94.144.9
 Traditional4.344.4244.465
NM (mV)
 Proposed143216104147148
 Traditional13917297173163

Different design corners are denoted by T: typical, F: fast, and S: slow.
Simulation condition: ,  V,  fF, and  µA.