MCML D-Latch Using Triple-Tail Cells: Analysis and Design

Table 4

Effect of process variation on the delay of the proposed and the traditional D-latch.

Parameter	NMOS
	T	F	S	F	S
	PMOS
	T	F	S	S	F
𝑡PD (ps)
Proposed	467	380	580	410	430
Traditional	589	565	984	587	590

Simulation condition: 𝐴_𝑣=4, 𝑉_SWING=0.4 V, 𝐶_𝐿=100 fF, and 𝐼_SS=100 µA.