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Active and Passive Electronic Components

Volume 2013 (2013), Article ID 574925, 9 pages

http://dx.doi.org/10.1155/2013/574925

## Additional High Input Low Output Impedance Analog Networks

^{1}Department of Electronics Engineering, Z. H. College of Engineering and Technology, Aligarh Muslim University, Aligarh 202002, India^{2}Department of Electronics and Communication Engineering, Jaypee Institute of Information Technology, Noida 201304, India

Received 6 June 2013; Accepted 14 August 2013

Academic Editor: Jiun-Wei Horng

Copyright © 2013 Sudhanshu Maheshwari and Bhartendu Chaturvedi. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

#### Abstract

This paper presents some additional high input low output impedance analog networks realized using a recently introduced single Dual-X Current Conveyor with buffered output. The new circuits encompass several all-pass sections of first- and second-order. The voltage-mode proposals benefit from high input impedance and low output impedance. Nonideality and sensitivity analysis is also performed. The circuit performances are depicted through PSPICE simulations, which show good agreement with theory.

#### 1. Introduction

In the recent past, realization of configurable analog networks has assumed special significance for modern analogue signal processing applications. The feature is quite suited while designing analog blocks with easy configurability, so as to be employed in field programmable analog arrays (FPAAs). Simple analog blocks with this feature were reported earlier and further researched in most recent works [1–3]. Whereas configurability gives rise to the possibility of several electronic functions from a single topology, cascadability results in practical utility of analog blocks for designing more complex networks without additional coupling elements in form of buffers [4–6]. The most recent analog circuit topology benefits from these features by being suited for a number of first-order electronic functions and offering high input impedance and low output impedance [5]. The two features together are just another step towards reducing circuit components enabling portable high performance systems with ease for FPAA implementations [7, 8]. It may be noted that analog filters continue to appear in open literature as a potential analog block for larger subsystems [2–6, 9–12].

This paper presents additional first- and second-order all-pass filters with the features of high input and low output impedance. State-of-the-art floating simulators have been employed to overcome the drawbacks of passive inductors [13]. It may be noted that floating inductor simulators using current conveyors have been researched well in the literature [14–17]. Transformation technique has further been employed to realize simpler alternative with lesser circuit complexity. Extensive simulations are performed to validate the proposed theory, which not only justify the proposed theory but also provide advancement to the existing knowledge.

#### 2. Additional First-Order All-Pass Filters

The symbol and CMOS implementation of newly developed second generation Dual-X Current Conveyor (DXCC-II) with buffered output are shown in Figure 1. A newly developed DXCC-II is characterized in matrix form by the following relationship: The new additional voltage-mode first-order all-pass filter topology is shown in Figure 2. It may be noted that interchanging the positions of and yields the topology of [5], a fact not mentioned therein. The given topology is characterized by the general transfer function for continual signals in “” domain as

Specialization of the impedances in Figure 2 yields missing circuits of voltage-mode first-order all-pass filters as listed in Table 1. The circuits of Filter 1 and Filter 2 use two passive components. In the circuit of Filter 1, and are retained with as a resistor and as a capacitor while open-circuiting and . In the circuit of Filter 2, and are retained with as a capacitor and as a resistor while open-circuiting and . No matching condition is required in both of the circuits of Filter 1 and Filter 2. In the last two circuits of Filter 3 and Filter 4 three components are used in each case. In the circuit of Filter 3, , , and are retained with , as capacitors and as a resistor while open-circuiting . In the circuit of Filter 4, , , and are retained with , as resistors and as a capacitor while open-circuiting . The circuits of Filter 1 and Filter 2 enjoy the advantage of single resistor control. The circuit of Filter 3 also enjoys the feature of single resistor control but is noncanonical. It also employs both capacitors in grounded form. The circuit of Filter 4 is canonical by employing single capacitor but requires matched grounded resistors. It is also to be noted that other useful first-order analog functions (e.g., lossy and loss less integrators, high pass filter, etc.) are also realizable from the modified general topology of Figure 2.

#### 3. Second-Order Filters

Selection of the impedances in Figure 2 yields a circuit of second-order voltage-mode all-pass filter by retaining all impedances , , , and . The selection of impedances is and as capacitive reactance as resistive, and is taken as inductive reactance . It is a well-known fact that real inductors are not used in integrated analog systems due to their bulky size, which became a motivating factor for the introduction of active-RC networks long back. In the circuit proposed here, simulated floating inductor [13] is used in place of the real inductor. The DXCC-II based circuit of [13] realizes a resistor less floating inductor. The new proposed voltage-mode second-order all-pass filter using simulated inductance is shown in Figure 3(a). Another circuit is obtained by interchanging the positions of the and terminals and is shown in Figure 3(b). The transfer function of the proposed circuits of Figures 3(a) and 3(b) is given as where for the circuit of Figure 3(a) and for the circuit of Figure 3(b).

The expressions for pole- and are given in (4) and (5), respectively: From (4) and (5), it is found that the can be tuned independent of by adjusting the value of .

Sensitivity figures for pole- and are given as follows: From (6), the sensitivity figures for the proposed circuits are found to be less than or equal to unity in magnitude which implies good sensitivity performance.

It is now to be emphasized that inductance simulator value is as , where and are transconductance of transistors used in simulated inductor, which can be controlled by the gate voltages of those transistors [13]. Here, is the transconductance of the th MOS transistor and is given as By substituting the value of in (3), the transfer function becomes The expressions for pole- and are also modified and given in (9) and (10), respectively: Sensitivity figures for pole- and are now given as follows: All the sensitivity figures given in (11) are still less than or equal to unity in magnitude, which suggests good sensitivity performance.

Another possible circuit design is to use frequency transformation method [18]. In frequency transformation, all the impedances are scaled by the frequency-dependent factor . Such an impedance-level scaling operation is quite appropriate, because this operation does not affect the transfer function. The motivation behind this scaling operation is that scaling inductive impedance by leaves the circuit with the resistor of the same value, , and the inductor is eliminated. However, so as not to change the transfer function in the scaling operation, all components must be scaled by the same factor. Therefore, the three passive elements are, namely, After transformation yields the new components Such scaling actually results in a transformation of the elements: a resistor becomes a capacitor of value “,” an inductor becomes a resistor of value “,” and a capacitor becomes a frequency-dependent negative resistor (FDNR) and is denoted by “” and symbolized as four parallel lines. The resulting circuit after frequency transformation is shown in Figure 4(a). Another circuit is obtained by interchanging the positions of the and terminals and is shown in Figure 4(b). Here, the active realization of FDNR using DXCC-II may be used [19]. The active realization of FDNR has the advantage of using a single active element and tunability by means of control voltage. The impedance function [19] is given for the ideal case for .

The transfer function of the proposed circuits of Figures 4(a) and 4(b) is given as where for the circuit of Figure 4(a) and for the circuit of Figure 4(b).

The expressions for pole- and are given in (15) and (16), respectively: Sensitivity figures for pole- and are given as follows: From (17), the sensitivity figures for the proposed circuits are all less than or equal to unity in magnitude which implies good sensitivity performance.

As an application of second-order voltage-mode all-pass filter, a sinusoidal oscillator producing two-phase signals is next given. The circuit is shown in Figure 5; it consists of a voltage-mode second-order all-pass filter and a unity gain inverter, with the output of the inverter being fed back to the input of the first stage. It may be noted that the inverter is realized using DXCC-II itself with input and output at and , respectively. The system loop gain (defined as , Figure 5) is given by If loop gain is set to unity at , the circuit shown in Figure 5 can be set to provide two-phase sinusoidal oscillation with oscillation frequency as The circuit provides two voltage outputs and . The voltage outputs marked in Figure 5 are related as .

#### 4. Nonideal Analysis

A nonideal DXCC-II is characterized by the following port relationship: Here, and are the current transfer gains from and terminals to and terminals, respectively, and are the voltage transfer gains from input terminal to and terminals, respectively, and is the voltage transfer gain from terminal to terminal (buffered output). However, these transfer gains are close to unity up to very high frequencies [20]. Using (20), the proposed circuits of voltage-mode second-order all-pass filter using simulated inductor as shown in Figures 3(a) and 3(b) are reanalyzed so as to yield the following voltage transfer function: where for the circuit of Figure 3(a) and for the circuit of Figure 3(b).

The expressions for pole- and are given as follows: Active and passive sensitivity figures for pole- and are given as Using (20), the proposed circuits of voltage-mode second-order all-pass filter using frequency transformation as shown in Figures 4(a) and 4(b) are reanalyzed so as to yield the following voltage transfer function: where for the circuit of Figure 4(a) and for the circuit of Figure 4(b).

The expressions for pole- and are given as follows: Active and passive sensitivity figures for pole- and Q are given as Equation (22) and (26) shows that the sensitivity figures are all less than or equal to unity in magnitude which implies good sensitivity performance. Sensitivity of filter parameters to current transfer gains will remain less than unity for the ideal value of current transfer gains which is equal to unity.

#### 5. Parasitic Considerations

The next study on the proposed circuits is carried out for the effect of parasitics involved with the used current conveyor. It assumes special significance for evaluating the real performance of any analog circuit. The various parasitics involved with a typical current conveyor [21] are well known to potential readers and will only be reviewed briefly. The various parasitics of the DXCC-II used in the proposed circuits are port parasitics in the form of , port parasitic in the form of and port parasitics. The proposed circuits are re-analyzed by taking into account the above parasitic effects. A re-analysis of the proposed circuit of voltage-mode second order all-pass filter using simulated inductor as shown in Figure 3(a) yields: where , , and .

From (27), it is clear that the parasitic resistances/capacitances merge with the external value. Such a merger does cause slight deviation in circuit’s parameters. It can be further observed from (27) that the order of transfer function of second-order all-pass filter is not changed. The modified expressions for pole- and with parasitic effects are also given as Next, it is seen from (28) that the pole frequency would slightly be deviated (in deficit) because of these parasitics. The expression showing the effects of parasitics on pole- is also given in (29). The pole- would also deviate slightly because of the parasitics. The deviation is expected to be small for an integrated DXCC-II.

#### 6. Simulation Results

The new proposed circuits are verified through PSPICE simulations. The simulations are based on 0.5 m, TSMC, CMOS parameters. Table 2 shows the dimensions of MOS parameters which are used in CMOS implementation of DXCC-II of Figure 1(b). The supply voltages used are ±2.5 V, , , and . The proposed voltage-mode second-order circuit of all-pass filter using simulated inductor has been designed at the pole frequency of 15.92 MHz. For the circuit of voltage-mode second-order all-pass filter (Figure 3(a)) resistance used is , capacitors used are of values , and, for the resistor less floating simulated inductor, the dimensions of the NMOS transistors are . The bias voltages are selected to be 0.78 V so as to obtain a resistance of 20 kΩ across each one of the MOS transistor. The capacitance is set to 2 pF so as to realize a floating inductance of 0.2 mH. The gain and phase response of the circuit of Figure 3(a) are shown in Figure 6, which shows the pole frequency as 15.85 MHz with a percentage error of 0.44%. The usefulness of new circuits is to be especially emphasized keeping in view the design frequency which is quite high. The input-output waveforms for voltage-mode second-order all-pass filter are shown in Figure 7. The Fourier spectrum of output is shown in Figure 8. The THD is found to be 1.5% which is also moderately low. The plot of THD variation at output with the amplitude of the input voltage is shown in Figure 9. Furthermore, the circuit of second-order voltage-mode all-pass filter using FDNR (Figure 4(a)) is also simulated. The gain and phase response of the circuit of Figure 4(a) are given in Figure 10. The circuit of Figure 4(a) was designed using , , and, for the realization of resistor less FDNR, the dimensions of the NMOS transistor are selected as = 4 m/1 m. The bias voltage is selected to be 1.2 V so as to obtain a resistance of 1.6 kΩ across the MOS transistor. The capacitances are set as and to realize FDNR1 and FDNR3 , respectively. The theoretical pole frequency used in this design was 25.18 MHz. The simulated pole frequency was found to be 25 MHz, which is very close to the theoretical value and only 0.71% in error.

The Monte Carlo analysis of the second order voltage-mode all-pass filter (Figure 3(a)) was next performed taking 5% Gaussian deviation in the each passive component (, , , and ). The analysis was done for 5 runs. The gain and phase response with Monte Carlo analysis is shown in Figure 11 and time domain result for Monte Carlo analysis is shown in Figure 12. As depicted from Monte-Carlo analysis results, the proposed filter has good sensitivity performances.

#### 7. Conclusion

This work presents four additional voltage-mode first-order all-pass filters and second-order all-pass filters with high input and low output impedance in each case. The circuits are based on the recently introduced active element, namely, Dual-X Current Conveyor with buffered output. As an application of the second-order voltage-mode all-pass filter, a voltage-mode oscillator configuration is given. Nonideal analysis of the proposed circuits is performed, and parasitic considerations are also discussed. The proposed circuits enjoy good active and passive sensitivities. Simulations results are given to confirm the presented theory.

#### Acknowledgments

The authors thank Academic Editor for recommending this paper. At the time of paper submission, the article processing charges for the Journal were waived off.

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