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Active and Passive Electronic Components
Volume 2013 (2013), Article ID 627873, 9 pages
A Novel Nanoscale FDSOI MOSFET with Block-Oxide
Department of Electrical Engineering, National Sun Yat-Sen University, No. 70 Lien-hai Road, Kaohsiung 80424, Taiwan
Received 9 October 2012; Accepted 28 November 2012
Academic Editor: Kuan-Wei Lee
Copyright © 2013 Jyi-Tsong Lin et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.
We demonstrate improved device performance by applying oxide sidewall spacer technology to a block-oxide-enclosed Si body to create a fully depleted silicon-on-insulator (FDSOI) nMOSFET, which overcomes the need for a uniform ultrathin silicon film. The presence of block-oxide along the sidewalls of the Si body significantly reduces the influence of drain bias over the channel. The proposed FDSOI structure therefore outperforms conventional FDSOI with regard to its drain-induced barrier lowering (DIBL), on/off current ratio, subthreshold swing, and threshold voltage rolloff. The new FDSOI structure is in fact shown to behave similarly to an ultrathin body (UTB) SOI but without the associated disadvantages and technological challenges of the ultrathin film, because a thick Si body allows for reduced sensitivity to self-heating, thereby improving thermal stability.
Semiconductor science, triggered by the impetus of a growing market for faster, more reliable, and less costly chips, has been undergoing a rapid technological development . Many of these new technologies, however, suffer from undesirable side effects. For example, as the gate length of CMOS—the bulk complementary metal-oxide semiconductor—is decreased, short-channel effects (SCEs), such as drain-induced barrier lowering (DIBL) and threshold voltage () rolloff, become a significant problem because S/D encroachment begins to limit the gate’s ability to control the channel. Also, due to the existence of the PN junction between the Si substrate and the S/D regions, a large junction leakage current prevents the use of scaled-down transistors in low standby power (LSTP) applications. Moreover, the parasitic capacitance of the transistor may strongly affect the characteristics of CMOS devices [2–4]. Therefore, the use of planar technology for ultralarge-scale integrated (ULSI) circuits becomes more challenging.
Recently, silicon-on-insulator (SOI) technology has demonstrated promise for nano-CMOS scaling. Compared to its bulk Si counterparts, SOI offers reduced capacitance and lower OFF-state leakage current (), mainly due to the presence of a buried oxide (BOX) layer under the Si active layer . This can be attributed to the fact that the BOX can be seen as a “blocking layer” to reduce the drain electric field. Also, because the active region is fully isolated, it avoids the latch-up problem of classical CMOS devices.
The benefits of SOI technology, however, are not without associated problems. A partially depleted (PD) SOI transistor cannot achieve an improved performance in future sub-45 nm semiconductor devices, due to the electrical properties of PDSOI MOSFET relative to the thickness of the Si layer. It has been proved that a thick Si film makes reducing DIBL very difficult . The fully depleted (FD) ultrathin body (UTB) SOI MOSFET is able to improve the short-channel characteristics but suffers from high S/D series resistance, because the semiconducting Si layer is, by definition, ultrathin. Also, when the gate-to-source overdrive voltage () is high enough, the self-heating effect causes a negative incremental conductance in the UTBSOI MOSFET associated with thermal instability. Consequently, the reliability of SOI devices will be degraded by these issues [7–11].
Our previous studies revealed that some of the unique features of the FDSOI MOSFET with block-oxide (bFDSOI) could allow it to replace the UTBSOI structure for CMOS scaling [12–14]. The device parameters of bFDSOI and UTBSOI were not optimized; however, neither bFDSOI nor UTBSOI showed high drain ON-state current (). Now, equipped with a block-oxide-enclosed Si body using oxide sidewall spacer technology, this paper presents a fully depleted silicon-on-insulator (FDSOI) nMOSFET to improve device performance, without using ultrathin silicon film. Also, the authors have optimized the device parameters to enhance current drive without losing the desired electrical characteristics.
This paper is organized as follows: the device structures and their corresponding simulations are described in Section 2. In Section 3, the electrical characteristics are compared between the bFDSOI-FETs and their counterparts in the FDSOI-FET, UTBSOI-FET, and elevated S/D (E-S/D) UTBSOI-FET before a brief summary is carried out in Section 4.
2. Device Structures and Simulations
ISE-TCAD was used to design and simulate the thin S/D and the recessed S/D bFDSOI-FETs. The key steps for processing the bFDSOI are shown in Figure 1. First, the Si body was patterned with e-beam (see Figure 1(a)), and for thin S/D bFDSOI-FET, 60 nm thick oxide was deposited using chemical vapor deposition (CVD) as a blocking layer. The deposited oxide layer was then etched back to form the sidewall spacers of the Si body (see Figure 1(b-1)). A layer of poly-Si (5 nm thick) was then deposited to act as an active layer (see Figure 1(c-1)). For the recessed S/D bFDSOI-FET, a 15 nm thick oxide was deposited and etched back to form the sidewall spacers of the Si body (see Figure 1(b-2)). Next, poly-Si was deposited and planarized with chemical mechanical polishing (CMP). Poly-Si (5 nm thick) was then redeposited to form the active region (see Figure 1(c-2)). For both bFDSOI-FETs, a 2.3 KeV boron difluoride (BF2) channel implantation at a dosage of 1.15 × 1012 cm−2 was performed, followed by rapid thermal annealing. Hence, the values of for both devices were determined. Then, 1.4 nm thick oxide was grown and a 50 nm thick poly-Si layer was deposited, followed by gate patterning. After gate patterning, a layer of nitride was deposited and etched back by dry etching. Next, 10 nm oxide was deposited as an implantation screen layer. In order to form S/D regions for bFDSOI-FETs, arsenic ions were implanted at a dosage of 2.1 × 1014 cm−2 and an ion implantation energy of 14 KeV, followed by thermal annealing. As a result, the source/drain resistance for both devices was determined playing an important role in drain currents. The second sidewall spacers were then formed by dry etching. After contact formation, bFDSOI-FETs were achieved.
In this paper, some technical “tricks”, such as S/D extension (SDE) implants , asymmetric halo , and retrograde channel profiles , were not used for our bFDSOI-FETs because the purpose of this work is to emphasize the importance of the block-oxide in reducing the SCEs. The device parameters used are listed as follows. For thin S/D and recessed S/D bFDSOI-FETs, typical values of Si body thickness () and poly-Si channel thickness () were 30 nm and 5 nm, respectively. Additionally, three types of SOI MOSFETs (FDSOI, UTBSOI, and E-S/D UTBSOI) were designed; the parameters were based on the same conditions for the simulation. For the FDSOI-FET, the typical value of is 30 nm. For the UTBSOI-FET, the typical value of (= ) is 5 nm. For the E-S/D UTBSOI-FET, the typical value of (= ) is 5 nm, and the raised S/D thickness is 35 nm. The other parameters, BOX thickness () and front-gate oxide thickness () are 50 nm and 1.4 nm, respectively.
3. Results and Discussion
The physics models in this paper, including the generation and recombination model, the effective intrinsic density model, and the basic mobility models, were specified for the characteristics of bFDSOI-FETs and its counterparts. Among them, the mobility models include a doping-dependence model and a high-field-saturation model (velocity saturation for electrons), based on the hydrodynamic Canali model. Besides the models used in simulation, a local-carrier temperature-dependent impact-ionization model is attached to the generation and recombination models, a transverse-field dependence model is attached to the basic mobility models, and a hydrodynamic model is used to simulate numerically the characteristics of bFDSOI-FETs and its counterparts .
For bFDSOI-FETs, owing to the presence of single crystal Si body, the poly-Si active layer can be recrystallized after annealing. In the simulation study, the crystalline Si values used for bFDSOI-FETs were the same as those used for FDSOI and UTBSOI devices. The major parameters for the comparison are listed as follows. is the voltage bias applied between drain and source, is the linear threshold voltage at V, and is the saturation threshold voltage at V. The threshold voltage is extracted using the constant current method at μA/μm. The saturation current () is the drain current at V. The leakage current () is the drain current at V and V. DIBL is the difference between the and the . In order to adjust the and optimize the , the barrier of doped poly-Si (gate electrode) is chosen as 0.45 eV because this is the difference between the poly-Si extrinsic Fermi level and the Si intrinsic Fermi level .
Figure 2 shows the surface potential plots for both the bFDSOI and SOI MOSFETs with gate length of nm. As shown in Figure 2, there is no significant change in the potential for bFDSOI-FETs as increases, although a slight change in the potential is observed. However, the FDSOI MOSFET (green line) still shows an increase due to the SCEs. This means that the thick FD scheme cannot effectively handle the issue of DIBL. These results confirm that the influence of drain bias upon the channel current has been reduced. As a consequence, the block-oxide-enclosed Si body helps suppress the SCEs, leading to an improved subthreshold swing and a decrease in . Unfortunately, the appears to drop across the S/D regions rather than the channel regions, which leads to smaller effective which then drops across the channel region. This is not the ideal condition for a comparison of the properties of the intrinsic devices designed. The reason for this is that we have not optimized the S/D engineering in this study so that the characteristics are strongly dependent on the source/drain parasitic resistances. However, this study does predict the general trends for device scaling. Figure 3 shows the transfer characteristics of FETs with gate length nm. Because of the block-oxide-enclosed Si body, bFDSOI-FETs show that DIBL is suppressed and subthreshold swing is improved. Furthermore, both thin S/D and recessed S/D bFDSOI-FETs show similar results compared to the UTBSOI-FET as well as the E-S/D UTBSOI-FET—additionally, those results are all better than those for the FDSOI-FET. In the UTBSOI-FET or E-S/D UTBSOI-FET, the subthreshold leakage current is the lowest among the transistors. Although FDSOI-FET shows the highest and transconductance ( in Figure 4), it is very difficult to alleviate the SCEs in a thick body structure. For a given MOS device, transconductance is proportional to the square root of the drain-to-source current . This suggests that thick S/D regions need to be introduced for an SOI to reduce series resistance. Yet a thick S/D structure alone cannot effectively reduce SCEs. Note that in Figure 5, the DIBL of bFDSOI-FETs is much smaller than that of the FDSOI-FET because the influence of drain bias on the channel current is reduced, as discussed earlier. Also, Figure 5 shows that as the gate length is reduced, the DIBL characteristics of the thin S/D bFDSOI-FET become slightly better than the recessed S/D bFDSOI-FET because the thin S/D structure possesses an effective method of suppressing SCEs. Nevertheless, either of the bFDSOI-FETs can alleviate the requirement of using an ultrathin channel to control SCEs in future nanodevices.
Figure 6 shows the versus for the MOSFETs at different gate lengths. Thanks to its improved subthreshold swing, the bFDSOI-FETs show a lower when compared with the FDSOI-FET. It should be noted that the FDSOI-FET shows the highest among transistors. As discussed earlier, thick S/D structure alone was unable to effectively reduce source and drain punch-through leakage, leading to the increase in . On the one hand, UTBSOI-FET achieves the lowest , mainly owing to the ultrathin S/D structure that suppresses punch-through and reduces the leakage current. This ultrathin S/D structure also allows the UTBSOI-FET to better control SCEs (see Figure 3), by reducing the effects of charge sharing. But the UTBSOI-FET has a poor because of the high series resistance caused by its ultrathin S/D regions. In the case of the E-S/D UTBSOI-FET, due to the nonoptimized S/D doping (because we use the same process conditions and parameters to fabricate all devices except those unique respective structures), this results in the longest channel length among all five transistors, and a poor is obtained. That is why the E-S/D UTBSOI-FET shows a better subthreshold swing and lower leakage current compared to the UTBSOI-FET as also shown in Figure 3 and smaller DIBL with decreasing gate length as shown in Figure 5. Therefore, the long channel leads to the small channel current and transconductance as shown in Figure 4. Both of the bFDSOI-FETs have similar results to the UTBSOI-FET. This is because the combined applications of a thick Si body and a block-oxide in a FDSOI MOSFET are used to minimize the effects of charge sharing.
Figure 7 shows the S/D series resistance () for the different transistors, which was extracted at V and V . Compared with the thin S/D bFDSOI-FET and the UTBSOI-FET, both of the recessed S/D bFDSOI-FET and the FDSOI-FET have a very low because of their thick S/D regions. Furthermore, owing to the raised S/D scheme, the E-S/D UTBSOI-FET reveals a similar when compared to the recessed S/D bFDSOI-FET. We also consider that due to the recessed S/D scheme, the bFDSOI-FET can get a relatively lower than that of the E-S/D UTBSOI-FET. In other words, the junction depth that is different for both devices may be a reason why the of the recessed S/D bFDSOI-FET is relatively smaller. The low is desirable for SOI devices in high-performance applications, but ultrathin S/D regions have difficulty achieving a low . Although the FDSOI-FET shows the lowest among the transistors, it is difficult to reduce DIBL and other SCEs. For the recessed S/D bFDSOI-FET, the combined applications of a thick S/D and a block-oxide are an effective way of reducing as well as DIBL. For the thin S/D bFDSOI-FET, it is difficult to reduce because of its thin S/D regions, but the thinness of these regions makes it easy to reduce DIBL. On the other hand, the E-S/D UTBSOI-FET also exhibits a smaller compared to the UTBSOI-FET; however, the Miller capacitance is one of the most important issues for high-frequency applications.
The subthreshold swing and of MOSFETs, as a function of the gate length, are presented in Figure 8. Because of the good gate controllability over the active channel, the bFDSOI-FET has an improved subthreshold swing and a better rolloff when compared with the FDSOI-FET. According to recent trends, SOI FETs limit the device performance itself since a uniform film thickness below 10 nm is needed for improving the subthreshold swing [21, 22]. In brief, SOI devices need to conform to the rule that . The use of a block-oxide in FDSOI design can alleviate the requirement for a uniform ultrathin Si film, thereby making the characteristics of the bFDSOI-FETs like those of the UTBSOI-FET with or without an E-S/D scheme, even though the total body thickness (including the single crystal Si body and the poly-Si film deposited afterward) is 35 nm in the bFDSOI-FETs.
One of the key issues associated with SOI-based transistors is self-heating effects (SHEs), because the reliability of SOI devices is severely affected by thermal instability. To investigate the influence of SHEs on the device structures, various gate-to-source overdrive voltages () are applied to the devices. With V, thin S/D bFDSOI-FET still shows good behavior in suppressing SHEs. However, FDSOI, UTBSOI, and E-S/D UTBSOI devices, in contrast, suffer from serious thermal effects because the self-heating-induced negative differential conductance (NDC) is observed in the output curves, as shown in Figure 9. The authors also found that the 35 nm thick body bFDSOI structures can help transistors to endure more heat generated in the channel. Although the body of the FDSOI is thicker than that of the UTBSOI, a higher drain current also results in more heat energy and eventually leads to a reduction of the drain current when the FDSOI enters into the saturation region. For the recessed bFDSOI-FET, due to the higher drain current compared to that of the thin S/D bFDSOI-FET, the self-heating-induced NDC is also observed in the output curves. However, the recessed S/D bFDSOI-FET still provides better self-heating immunity than SOI devices owing to its thick body scheme. Additionally, due to the lower current in the bFDSOI device than in the UTBSOI, self-heating is not dominant. If the drain current is high enough, self-heating is still a significant problem for the bFDSOI-FETs, as it is in UTBSOI devices. Nevertheless, owing to the thick body and the block-oxide schemes, requiring a uniform UTB structure for suppression of SCEs can be excluded. This relaxes the technology requirement in a UTB application. In addition, the power supply voltage will eventually decrease in order to reduce the power consumption in the IC circuits. Therefore, the thermal instability in the bFDSOI-FETs can be diminished via a choice of low power supply (i.e., ).
In the case of low drain bias, self-heating is not significant; hence the NDC is not obviously observed in the output characteristics. The better control of SCEs the transistor has, the higher output resistance () the transistor possesses. That is why the UTBSOI with or without an E-S/D structure can produce a higher compared to the FDSOI, with or without a block-oxide scheme. In addition, because large drain current results in large , both FDSOI and recessed bFDSOI devices show a larger than those of other transistors. In order to compare the incremental voltage gain (), it is believed that the UTSOI with or without E-S/D devices can produce a higher voltage gain as compared to the FDSOI with or without block-oxide scheme, despite the fact that their is lower. It is because the poor short-channel behavior leads to a small observed in output curves for the FDSOI with or without the block-oxide scheme. If the self-heating is dominant, it is not a fair comparison chiefly owing to the NDC phenomenon that results in negative .
Figure 10 shows the electron temperature along the MOSFETs’ channel surface with gate length nm. For bFDSOI-FETs, the thermal stability can be improved with the addition of a thick body, which results in a lower electron temperature in the channel. Although an ultrathin S/D structure alone shows excellent subthreshold characteristics, SHEs will become a severe problem for SOI-based transistors in particular, as SHEs would likely block the use of SOI MOSFETs in high-performance CMOS applications. It is worthwhile noting that a high-temperature electron possessing high transportation, rotation, and vibration energy will result in the increased probability of phonon scattering and surface scattering, thereby increasing thermal resistance and aggravating self-heating. In contrast to both of these SOI-based transistors, bFDSOI-FETs can alleviate the requirement of uniform ultrathin films to control SCEs, thereby leading to high device reliability. As a result, the thermally induced vibrations of the atoms in the bFDSOI-FETs are ameliorated by its thick body. The body thickness of the FDSOI is thicker than that of the UTBSOI, but a higher also results in more heat energy and eventually leads to a serious reduction of the carrier mobility.
The simulation results in this paper suggest that a metal-gate material and a high-k dielectric should be introduced into the bFDSOI-FET devices. The use of a metal gate would allow the to be optimized even for a lightly doped ultrathin body. In addition, the metal gate, when used with a high-k dielectric, would allow the / ratio to be improved [24, 25]. This is because the work function of the metal gate can help transistors to adjust the while the high-k dielectric can also relax the requirement of ultrathin gate oxide to reduce the gate-tunneling leakage current.
Two important issues caused by the bFDSOI-FETs are addressed here: (1) the quality of poly-Si and (2) the non-self-aligned process. In the bFDSOI-FETs, the Si film used in this study for comparison is the same as that used in the FD and UTB SOI devices. The mobility of bFDSOI-FETs is actually affected by the poly-Si film. Although the lattice scattering caused by phonons in the bFDSOI-FETs can be reduced by its thick body, the poor quality of poly-Si also results in reduced mobility. Some methods of improving the quality of poly-Si are now described. In general, after making S/D regions by ion implantation, it is believed that poly-Si can be recrystallized because the poly-Si is directly connected to the single crystal Si body. Moreover, advanced recrystallization techniques can also be applied to the bFDSOI process to improve the quality of the poly-Si. Another key issue is the non-self-aligned process used in bFDSOI-FETs. In fact, self-aligned technology is not applicable in the bFDSOI-FETs presented. The misalignment problem will limit the bFDSOI-FETs’ performance. All of these issues, including the quality of poly-Si channel and the self-alignment of bFDSOI-FETs, will be addressed in our future research work.
In this paper a new planar FDSOI MOSFET with block-oxide has been presented and analyzed. The bFDSOI-FET is equipped with a block-oxide on the sidewall of Si body that helps improve the control of SCEs without requiring a uniform UTBSOI structure. As indicated by the two-dimensional (2D) simulation results, the authors found that the characteristics of the bFDSOI-FETs (a reduced DIBL, a higher on/off current ratio, an improved subthreshold swing, and a better rolloff behavior as compared with the FDSOI-FET) are similar to the UTBSOI-FET, because the block-oxide-enclosed Si body helps to diminish the influence of upon the channel current, resulting in desirable device characteristics. Although the short-channel properties of bFDSOI-FETs are somewhat worse than those of UTBSOI-FETs, the results are acceptable. Moreover, both types of bFDSOI-FETs also exhibit significantly lower channel temperature due to their thick bodies. It should be noted that this thick body, including the single crystal Si body and the poly-Si film deposited afterwards, are used to tolerate much of the heat being generated in the channel when compared with the UTBSOI-FET. As a result, the thermal stability of the bFDSOI-FETs can be improved by reducing the scattering of lattice atoms. Compared with the UTBSOI-FET, a thickness requirement of below 10 nm and uniform ultrathin film are excluded for the bFDSOI-FETs to diminish the charge-sharing effect without increasing self-heating. The bFDSOI-FETs are therefore found to improve the reliability of SOI CMOS devices and somewhat relax the critical technology requirement for potential applications.
- M. Quirk and J. Serda, Semiconductor Manufacturing Technology, Prentice-Hall, Englewood Cliffs, NJ, USA, 2001.
- M. J. Kumar and A. Chaudhry, “Two-dimensional analytical modeling of fully depleted DMG SOI MOSFET and evidence for diminished SCEs,” IEEE Transactions on Electron Devices, vol. 51, no. 4, pp. 569–574, 2004.
- O. Thomas, M. Belleville, F. Jacquet, and P. Flatresse, “Impact of CMOS technology scaling on SRAM standby leakage reduction Techniques,” in Proceedings of the IEEE International Conference on Integrated Circuit Design and Technology (ICICDT '06), pp. 2–6, May 2006.
- M. J. Kumar, V. Venkataraman, and S. K. Gupta, “On the parasitic gate capacitance of small-geometry MOSFETs,” IEEE Transactions on Electron Devices, vol. 52, no. 7, pp. 1676–1677, 2005.
- O. Faynot, T. Poiroux, F. Andrieu et al., “Advanced SOI technologies: advantages and drawbacks,” in Proceedings of the Extended Abstracts of the 6th International Workshop on Junction Technology (IWJT '06), pp. 200–203, May 2006.
- J. T. Lin, K. C. Lin, T. Y. Lee, and Y. C. Eng, “Investigation of the novel attributes of a vertical MOSFET with internal block layer (bVMOS): 2-D simulation study,” in Proceedings of the 25th International Conference on Microelectronics (MIEL '06), pp. 488–491, May 2006.
- Y. Omura, H. Konishi, and S. Sato, “Quantum-mechanical suppression and enhancement of SCEs in ultrathin SOI MOSFETs,” IEEE Transactions on Electron Devices, vol. 53, no. 4, pp. 677–684, 2006.
- S. Nuttinck, “Ultrathin-body SOI devices as a CMOS technology downscaling option: RF perspective,” IEEE Transactions on Electron Devices, vol. 53, no. 5, pp. 1193–1199, 2006.
- C. G. Ahn, W. J. Cho, K. J. Im et al., “Recesseed source-drain (S/D) SOI MOSFETs with low S/D extension (SDE) external resistance,” in Proceedings of the IEEE International SOI Conference, pp. 207–208, October 2004.
- K. Komiya, T. Kawamoto, S. Sato, and Y. Omura, “Impact of high-k plug on self-heating effects of SOI MOSFETs,” IEEE Transactions on Electron Devices, vol. 51, no. 12, pp. 2249–2251, 2004.
- Z. Sun, L. Liu, and Z. Li, “Self-heating effect in SOI MOSFET's,” in Proceedings of the 5th International Conference on Solid-State and Integrated Circuit Technology, pp. 572–574, October 1998.
- J. T. Lin, Y. C. Eng, K. D. Huang, T. Y. Lee, and K. C. Lin, “Ultra-short-channel characteristics of planar MOSFETs with block oxide,” in Proceedings of the 13th International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA '06), pp. 146–149, July 2006.
- J. T. Lin, Y. C. Eng, K. D. Huang, T. Y. Lee, and K. C. Lin, “A novel FDSOI MOSFET with block oxide enclosed body,” in Proceedings of the IEEE International Conference on Integrated Circuit Design and Technology (ICICDT '06), pp. 145–148, May 2006.
- Y. C. Eng, J. T. Lin, K. D. Huang, T. Y. Lee, and K. C. Lin, “An investigation of the effects of Si thickness-induced variation of the electrical characteristics in FDSOI with block oxide,” in Proceedings of the 8th International Conference on Solid-State and Integrated Circuit Technology (ICSICT '06), pp. 61–64, October 2006.
- E. Yuri and L. Jinning, “Precision implant requirements for SDE Junction Formation in sub-65 nm CMOS devices,” in Proceedings of the Extended Abstracts of the 6th International Workshop on Junction Technology (IWJT '06), pp. 21–24, May 2006.
- A. Bansal and K. Roy, “Asymmetric halo CMOSFET to reduce static power dissipation with improved performance,” IEEE Transactions on Electron Devices, vol. 52, no. 3, pp. 397–405, 2005.
- S. Venkatesan, J. W. Lutze, C. Lage, and W. J. Taylor, “Device drive current degradation observed with retrograde channel profiles,” in Proceedings of the International Electron Devices Meeting (IEDM '95), pp. 419–422, December 1995.
- User's Manual, ISE-TCAD, 2004.
- A. S. Sedra and K. C. Smith, Microelectronic Circuits, Oxford University Press, Oxford, UK, 4th edition, 1988.
- A. Dixit, A. Kottantharayil, N. Collaert, M. Goodwin, M. Jurczak, and K. De Meyer, “Analysis of the parasitic S/D resistance in multiple-gate FETs,” IEEE Transactions on Electron Devices, vol. 52, no. 6, pp. 1132–1140, 2005.
- H. Shang, J. Rubino, B. Doris et al., “Mobility and CMOS devices/circuits on sub-10 nm (110) ultra thin body SOI,” in Proceedings of the Symposium on VLSI Technology, pp. 78–79, June 2005.
- K. Samsudin, B. Cheng, A. R. Brown, S. Roy, and A. Asenov, “UTB SOI SRAM cell stability under the influence of intrinsic parameter fluctuation,” in Proceedings of the 35th European Solid-State Device Research Conference (ESSDERC '05), pp. 553–556, September 2005.
- S. Deleonibus, B. De Salvo, L. Clavelier et al., “CMOS devices architectures for the end of the roadmap and beyond,” in Proceedings of the 8th International Conference on Solid-State and Integrated Circuit Technology (ICSICT '06), pp. 51–54, October 2006.
- J. B. Kuo and C. H. Lin, “Capacitance behavior of nanometer FD SOI CMOS devices with HfO2 high-k gate dielectric considering gate tunneling leakage current,” in Proceedings of the 25th International Conference on Microelectronics (MIEL '06), pp. 59–61, May 2006.
- X. Yu, M. Yu, and C. Zhu, “Advanced HfTaON/SiO2 gate stack with high mobility and low leakage current for low-standby-power application,” IEEE Electron Device Letters, vol. 27, no. 6, pp. 498–501, 2006.