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Active and Passive Electronic Components
Volume 2013 (2013), Article ID 685939, 8 pages
Voltage-Mode Four-Phase Sinusoidal Generator and Its Useful Extensions
Department of Electronics Engineering, Z. H. College of Engineering and Technology, A.M.U., Aligarh 202 002, India
Received 19 February 2013; Revised 15 April 2013; Accepted 15 April 2013
Academic Editor: Ali Umit Keskin
Copyright © 2013 Sudhanshu Maheshwari. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.
This paper introduces a new voltage-mode second-order sinusoidal generator circuit with four active elements and six passive elements, including grounded capacitors. The frequency and condition of oscillation can be independently controlled. The effect of active element’s nonidealities and parasitic effects is also studied; the proposed topology is good in absorbing several parasitic elements involved with the active elements. The circuit is advantageous for generating high frequency signals which is demonstrated for 25 MHz outputs. Several circuit extensions are also given which makes the new proposal useful for real circuit adoption. The proposed theory is validated through simulation results.
Four-phase sine-wave generators with voltage outputs progressively separated by 90° apart find useful applications in communication and instrumentation systems and hence have been well covered in open literature [1–4]. Some of the earlier works based on transconductance- approach  offered compact realization with low transistor counts, but limited in frequency when compared to current conveyor based works . Very novel addition to the literature witnessed compact bread-boarding solutions with scope of future integration of new active elements, like DO-CIBA . Meanwhile, traditional approach of employing band-pass filter for quadrature oscillator realization, capable of generating four-phase outputs, continues to attract recent attention . The four-phase voltage-mode circuit of  uses five opamps and five passive components, most of which are in floating form. The works as mentioned so far [1–5] falls in the category of second-order networks. Another variety of circuits employed third-order networks to generate quadrature voltage outputs, with a possibility of extension to four phases by additional active elements . The active- network of  used current controlled conveyors and three capacitors. Though the circuit in  was intended to generate four-phase current outputs, two quadrature voltage outputs were simultaneously available, a fact not mentioned therein. The discussion on quadrature oscillators’ review is worth a voluminous work and can be restricted here, in view of a recent work [3, and cited therein]. In spite of this restriction, there are many works which find mention for their value, without belittling hundreds of other works, not mentioned herein [7–14]. For instance the work in  was a first attempt to use DVCC for oscillator application. Another work later  presented voltage-mode quadrature oscillator based on two DDCC and five grounded passive components, which can be extended for four phases by employing additional active building blocks.
This work is based on the realization of four-phase voltage-mode oscillator employing band-pass filter as reported in a recent work . Although, the available work proposed a four-phase oscillator with voltage outputs, which was based on a third-order network , the new proposed circuit is based on a second-order network, thus providing a new unreported solution with effective results. The proposed circuit is based on four differential voltage current conveyors (DVCCs), four resistors, and two capacitors, unlike the available work, where three resistors and capacitors each were used . The similarity of the new proposed circuit with available one  may only be deceptive, since the two works differ in order by “one,” as also mentioned in the following. Circuit parasitic considerations, nonideal issues, and circuit variations along with the workability are given to support the technical novelty of the proposal.
2. Circuit Description
The proposed voltage-mode four-phase sinusoidal generator circuit is based on DVCCs, whose symbol and circuitry are shown in Figure 1, followed by the actual oscillator circuit in Figure 2. The DVCC of Figure 1 is described by the relationship It may be noted that the circuit of DVCC with only + stage requires 12 transistors only and can be used as DDCC, by ungrounding the gate of , naming it as , with the modified , along with . The DVCC/DDCC based analog circuit design continues to be a favorable research topic till recently [4, 16–18]. The basic scheme along with the proposed circuit is shown in Figures 2 and 3, respectively. The circuit requires four active elements and six passive elements, with the advantage of both grounded capacitors. Inverting band-pass transfer function of the basic scheme of Figure 2 is realized from node of DDCC-1 to node in Figure 3. The inverting gain factor (-) of Figure 2 is realized using DVCC-4 along with and in Figure 3. It may be noted that the inverting amplifier used is one of the several analog blocks as available in . It may be noted that the DDCC-1 has unused terminal, which need not to be implemented, thus reducing the implementation of DDCC-1 by two transistors. Routine analysis of the circuit of Figure 3 (along with the block diagram of Figure 2) yields the following characteristic equation: The frequency of oscillation (FO) and the condition of oscillation (CO) are found from (3) as follow: Equation (3) can be easily interpreted for the variation of FO independent of CO, by the frequency determining passive components; whereas, the CO requires setting of separate resistors. The four-phase voltage outputs are related as follows: At the frequency of oscillation, the previous equation can be expressed as follows: For a design with equal resistors () and equal capacitors (), the angular frequency of oscillation is obtained from (3) as ; then (5) reduces to Equation (6) shows equal amplitudes for the four outputs, which are separated in phase progressively by 90°.
3. Parasitic Considerations
The circuit of Figure 3 is next analyzed for the involvement of DVCC parasitic elements. It is a well-known fact that the parasitic effects are circuit-topology dependent. A current conveyor circuit with resistive terminations is suited for absorbing the terminal intrinsic resistance (), although the net value does increase by . Similarly, a current conveyor-based network with capacitive terminations at and/or terminals is good from the point of absorption of parasitic capacitance at these terminals ( and/or , resp.), though the net value at those nodes does increase. Resistive terminations at terminal with moderate design values (few KΩ’s) also does not hinder the circuit behavior much from the ideal, as the parasitic resistance at () is relatively much higher than the externally connected resistor, appearing in shunt. Coming to the circuit of Figure 3, it may be noted that the various external passive elements are modified due to the parasitics as follows: The nonideal FO and CO are thus found as follows: Equations (7)-(8) suggest that the actual FO would be slightly smaller than the desired FO, but the circuit topology does provide the designer scope of nullifying the parasitic effects, by predistorting the passive components. The actual errors as a result of parasitic elements would be given in the results’ section.
4. Nonideal Transfer Gain Effects
A nonideal DVCC is characterized by the following relationship:
Here, the voltage transfer gains from , , to terminal is denoted by , and current transfer gain form terminal to + terminal is . The proposed circuit’s topology (Figure 3) is such it nullifies the transfer gain effect from to , thus easing the nonideal expression rid of . An analysis of the circuit using the nonideal description yields the oscillator’s characteristic equation as follows: It may be noted that the for different DVCCs is taken identical to simplicity of the expression, thus dropping the suffix. The nonideal FO and CO in light of the previous equation thus become Equation (11) needs to be first interpreted in terms of frequency errors, as the numerator would be slightly smaller than the ideal expression (3), thus causing a decrement in the actual frequency of oscillation in comparison to the designed value. A similar effect was found in previous section after incorporation of parasitic elements. Thus it is to be appreciated that the FO would be slightly smaller than the desired value, to be further commented upon in results’ section. Secondly, (11) has been derived with the assumption that the transfer gains for various DVCCs would be identical, which is quite practical, especially for integrated realizations. Now, the appearance of with power 3/2 may be quite annoying from sensitivity perspective, but actually it is equal to three different s for different conveyors. With this clarification, the sensitivity of FO with respect to all active and passive elements is found to be within unity in magnitude, ensuring good performance.
5. Verification Results
The four-phase oscillator of Figure 3 was simulated using the DVCC of Figure 1 using PSPICE tool. The parameters’ details are listed in many recent works, hence not repeated here [14, 15]. The circuit was designed with capacitive elements of 10 pF and frequency determining resistors () as 3 KΩ, thereby yielding a theoretical frequency of oscillation as 10.6 MHz from (3). The CO was adjusted through setting in the vicinity of 4 KΩ, retaining KΩ. The output waveforms are shown in Figure 4, where the FO is found as 10.25 MHz, resulting in an error in FO of approximately 3%. The spectrum of the four outputs is shown in Figure 5; the THD is found to be around 1.1%. The proposed circuit provides interesting options for tunability through either and/or without restriction on their ratios or involvement in CO, a preferred method exhibited in most of the related literatures on the subject. However, the circuit topology used  has a scope of being used as a potential analog cell for field programmable analog arrays, where programmable capacitor arrays are employed. In such applications, an array of equal capacitors is available, which need to be switched so as to vary a circuit parameter. With this view, the tunability of the proposed oscillator is studied by using capacitive elements of values 8 pF, 6 pF, and 4 pF so as to result in FO as 12.5 MHz, 17.5 MHz, and 25 MHz, respectively. The spectrum of the output waveforms is shown in Figure 6, which confirms the practical utility of the proposed circuit.
6. Circuit Extensions
This section presents some useful circuit extensions by simple modifications to the proposed circuit of Figure 3. Several variations with distinct features are given as useful future adoptions.
6.1. Eight Outputs’ Circuit
The voltage-mode four-phase oscillator of Figure 3 can be extended for explicit four-phase current outputs by employing -stages. Additional + and stages incorporation in DVCC-2 and DVCC-3 each result in four current outputs spaced progressively 90 degrees apart. With this modification (addition), the circuit can be used as a complete four-phase oscillator with both voltage as well as current outputs. The resulting circuit is unique in light of the available literature, by simultaneously generating eight outputs in all. The previously referred circuit (with eight outputs capability) is also simulated to support the theory. Additional + and stages each in DVCC-2 and DVCC-3 are implemented so as to result in four-phase current outputs. For the presentation of results, the stages are incorporated in the above-mentioned conveyors so as to generate the quadrature current outputs as shown in Figure 7, with the same design as given earlier for voltage outputs. The Fourier spectrum is next shown in Figure 8, with the FO as 10.25 MHz. It may again be noted that two additional outputs (phase inverted with respect to the ones shown in Figure 7) would be available at + terminals of the conveyors.
6.2. Circuit with Simpler Configuration
Circuit with simpler configuration can be obtained by leaving the terminal unused while retaining the circuit’s functionality. This modification results in an FO half of what is obtained for Figure 3, and the CO reduces to . The resulting circuit is simpler in the sense that stages need not to be implemented (please note that current outputs as mentioned in following section will not be available here). More importantly, the parasitic capacitance in (7) disappears as a result of this modification, enabling reduction in errors in FO, for a given capacitor (, ) based design as compared to the circuit of Figure 3. This also provides a design guideline to use smaller capacitance-based design for a permissible FO error. On the other hand, in order to obtain the same FO range as in circuit of Figure 3, the modified circuit would necessitate smaller resistance values, which makes “” induced error more influential, when compared to the circuit of Figure 3. Such discussions often lead to unending arguments, best attributed to the artistic mysteries of analog circuit design. Notwithstanding, newer topologies are actually synthesized, as a result of such discussions.
6.3. Circuits with Tunable DVCCs
Another circuit enhancement is the use of voltage controlled DVCC as was introduced in . In such case, the -terminated resistors are eliminated, and instead the intrinsic terminal resistance becomes effective, which is tunable through the bias voltage as has been shown in . Though limited tenability is achieved, the circuit does become a voltage controlled oscillator. Alternatively, current controlled DVCCs can be employed in place of conventional DVCCs. The terminal resistors are again replaced by intrinsic resistance. The circuit’s frequency of oscillation can then be tuned through the bias currents. However, the relative complexity involved will almost double, as the CC-DVCC is a combination of CCCII and DVCC, as has been very well demonstrated in some useful novel works [20, 21].
6.4. Use of Current Gain Variable DVCC
Very interesting circuit advancement can be obtained by employing current gain variable DVCCs. It may be noted that conventional DVCC has unity current transfer gain from to terminal. This may be varied to obtain a current-gain variable DVCC. The concept of current-gain variable current conveyors has its origin from some earlier works [22–25]. The proposed circuit of Figure 3 is a promising candidate for the purpose, as is evident from the nonideal expressions (10)-(11). These suggest that the oscillator’s frequency and condition are a function of current transfer gain “.” If is made variable, then the FO can be tuned through it, rather than the external passive elements. A simple way to achieve this is to vary the aspect ratio of transistors comprising the stage as was also given in , but for amplitude control in that particular work. A more practical way is to tune the current gain and hence the frequency of the oscillator by digital means as given in the following.
6.5. Digitally Controlled Circuit
A last future enhancement is the use of a digitally controlled current transfer gain stage, which has been recently employed in some work [26, and cited therein]. The current transfer gain “” can be digitally controlled through an -bit control work so as to vary the frequency of the oscillator. In such an oscillator, none of the external passive elements need to be varied for frequency tuning. The complete circuit digital control and analog can thus be made compatible to standard IC technologies. Further details of the above-mentioned circuit extensions are not to be further elaborated for brevity reasons.
7. Some Interesting Remarks
The topic of this paper assumes significance in light of some interesting works which continue to appear till recently in the open literature [27, 28]. As far as the quadrature oscillator’s (with two quadrature outputs) extension to four outputs is concerned, additional inverters can be employed in such cases. A DVCC with input voltage at and the output at (with rest unused terminals) can perform the function of an inverter. The terminal resistance () along with output capacitance () by way of forming a low-pass filter (lossy integrator) results in finite (although) high pole frequency, thus in a way limiting high frequency operation with poorer THD, as compared to the proposed circuit, where lossless integrators provide infinite pole frequency. Thus the distortions at high frequency would not be as much in the proposed circuit as in a quadrature oscillator with inverters to generate four signals. This justifies the use of the proposed structure, as compared to the one with additional inverters. Coming to the possible application of quadrature oscillators, their utility in quadrature mixers, single sideband generation vector voltmeters, and so forth have often been highlighted in literature. The circuits with quadrature outputs along with their inverted versions (four phases) are of special interest as two floating output sources of quadrature signals. In such an application, the circuit can also be referred to as a differential output quadrature oscillator. Other possible applications of four-phase quadrature signals can be in quadrature phase shift keying, as well. Besides, when four quadrature signals are passed through comparators, they become a source of four-phase clock generators. In nutshell, the proposed circuit and their extensions presented in the preceding section cover useful application areas.
The paper deals with a new proposal for voltage-mode four-phase oscillator circuit with independent control of FO as well as CO and use of grounded capacitors and a circuit topology suited to minimizing the parasitic effects and applicability to high frequency. Nonideal and parasitic study is also given. Some useful circuit extensions for a simpler topology, for simultaneous four-phase current outputs, voltage/current tunable oscillator, and digitally controlled circuit are also given. The new proposals are enrichment to the available knowledge on the subject.
The author is thankful to the anonymous reviewers for positive feedback on the paper. The author also thanks Professor Ali Umit Keskin, Academic Editor, for recommending the paper.
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