Modeling of the Channel Thickness Influence on Electrical Characteristics and Series Resistance in Gate-Recessed Nanoscale SOI MOSFETs

<table>Cross-view of a TCAD (Tsuprem4) simulated nanoscale devices using the gate-recessed channel process. The layers deposition sequence is described in the text.</table>

Active and Passive Electronic Components

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Figure 3

Figure 3: Modeling of the Channel Thickness Influence on Electrical Characteristics and Series Resistance in Gate-Recessed Nanoscale SOI MOSFETs 