Modeling of the Channel Thickness Influence on Electrical Characteristics and Series Resistance in Gate-Recessed Nanoscale SOI MOSFETs

Figure 6

Semilog plot of 𝑅_SD0 and 𝜇_eff versus channel thickness for four NSB devices (dices E15, C12, G15, and C03) having a channel thickness (𝑡_SI) of 1.6, 2.4, 2.9, and 4.9 nm, respectively. 𝑅_SD0 is extracted from Figure 4 as the ratio of the 𝑉_DS constant value (0.1 V) to the drain current measured at zero 𝑉_GS. 𝜇_eff is extracted from (2).