Modeling of the Channel Thickness Influence on Electrical Characteristics and Series Resistance in Gate-Recessed Nanoscale SOI MOSFETs

Table 1

Process parameters for deposited layers.

Layer number	Layer name	Layer acronym	Layer thickness [nm]	Function and properties
01	Bulk silicon	Bulk		Substrate p-type (10^15 cm^−3); Resistivity: 14–22 Ω · cm; Orientation ⟨100⟩
02	Buried oxide	BOX	70	Bulk insulator; O^+ implantation energy: 120 keV (2.35 hours); Dose: 0.39 10^18 O^+/cm^2; Anneal: 1320°C (6.00 hours)
03a	Silicon-on-insulator	SOI	46	p-type (10^15 cm^−3) regular transistor channel in UTB devices and nonreduced SOI in NSB devices (source-drain extensions)
03b	Gate-recessed silicon	GRS	1.6–6.5 range	Thinned transistor channel in NSB devices
03c	Pad oxide	PAD OX	15	Relieve stress from silicon to nitride at high temperature
04	Gate oxide	GOX	26	Gate insulator
05	Polysilicon	Poly	220	Gate electrode
06	Nitride 2	Nit	30	Prevent further oxidation of the thin silicon layer during the implant's thermal annealing (NSB)
07	Field oxide	FOX	700	Active area insulator
08	Silox	SOX	350	Contact opening mask for source/drain and gate passivation
09	Polysilicon	Poly	220	Source/drain polycontacts; Source/drain doping obtained by phosphorous implant; Dose D = 2.5 10^15 cm^−2Energy E = 30 keV; HTA High temperature annealing T = 1000°C, (30 min)
10	Aluminum	Al	500	Source/drain metal contacts