About this Journal Submit a Manuscript Table of Contents
Active and Passive Electronic Components
Volume 2013 (2013), Article ID 839198, 9 pages
http://dx.doi.org/10.1155/2013/839198
Research Article

Circuit Implementation, Operation, and Simulation of Multivalued Nonvolatile Static Random Access Memory Using a Resistivity Change Device

1Faculty of Medicine, Graduate School of Medical Science, Kanazawa University, 5-11-80, Kodatsuno, Kanazawa 920-0942, Japan
2Faculty of Engineering, Graduate School of Natural Science & Technology, Kanazawa University, Kakuma, Kanazawa 920-1192, Japan

Received 21 June 2013; Revised 15 October 2013; Accepted 15 October 2013

Academic Editor: Ezz I. El-Masry

Copyright © 2013 Kazuya Nakayama and Akio Kitagawa. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Linked References

  1. S. Eaton, D. Butler, M. Parris, D. Wilson, and H. Mcnellie, “A ferroelectric nonvolatile memory,” in Proceedings of the International Solid-State Circuits Conference(ISSCC '88), pp. 130–131, 1988.
  2. S. Masui, T. Ninomiya, T. Ohkawa et al., “Design and application of ferroelectric memory based nonvolatile SRAM,” IEICE Transactions on Electronics, vol. E87-C, no. 11, pp. 1769–1776, 2004. View at Scopus
  3. M. Takata, K. Nakayama, T. Izumi, T. Shinmura, J. Akita, and A. Kitagawa, “Nonvolatile SRAM based on phase change,” in Proceedings of the 21st IEEE Non-Volatile Semiconductor Memory Workshop (NVSMW '06), pp. 95–96, February 2006. View at Publisher · View at Google Scholar · View at Scopus
  4. S. Yamamoto and S. Sugahara, “Nonvolatile static random access memory using magnetic tunnel junctions with current-induced magnetization switching architecture,” Japanese Journal of Applied Physics, vol. 48, no. 4, Article ID 043001, 2009. View at Publisher · View at Google Scholar · View at Scopus
  5. A. Kitagawa and K. Nakayama, “Phase change nonvolatile SRAM and Resister',” in Proceedings of the 21th Symposium on Phase Change Optical information Storage (PCOS '09), pp. 33–36, 2009.
  6. J. Maimon, E. Spall, R. Quinn, and S. Schnur, “Chalcogenide-based non-volatile memory technology,” in Proceedings of the IEEE Aerospace Conference, vol. 5, pp. 2289–2294, March 2001. View at Scopus
  7. K. Nakayama, M. Takata, T. Kasai, A. Kitagawa, and J. Akita, “Pulse number control of electrical resistance for multi-level storage based on phase change,” Journal of Physics D, vol. 40, no. 17, article 009, pp. 5061–5065, 2007. View at Publisher · View at Google Scholar · View at Scopus
  8. Y. Yin, K. Ota, T. Noguchi, H. Ohno, H. Sone, and S. Hosaka, “Multilevel storage in N-doped Sb2Te3-based lateral phase change memory with an additional top TiN layer,” Japanese Journal of Applied Physics, vol. 48, no. 4, Article ID 04C063, 2009. View at Publisher · View at Google Scholar · View at Scopus
  9. S. Lee, J.-H. Jeong, T. S. Lee, W. M. Kim, and B.-K. Cheong, “Bias polarity dependence of a phase change memory with a Ge-doped SbTe: a method for multilevel programing,” Applied Physics Letters, vol. 92, no. 24, Article ID 243507, 2008. View at Publisher · View at Google Scholar · View at Scopus
  10. Y. Han, K. Cho, and S. Kim, “Characteristics of multilevel bipolar resistive switching in Au/ZnO/ITO devices on glass,” Microelectronic Engineering, vol. 88, no. 8, pp. 2608–2610, 2011. View at Publisher · View at Google Scholar · View at Scopus
  11. S. Kawabata, M. Nakura, S. Yamazaki et al., “CoOx-RRAM memory cell technology using recess structure for 128Kbits memory array,” in Proceedings of the IEEE International Memory Workshop (IMW '10), pp. 16–19, May 2010. View at Publisher · View at Google Scholar · View at Scopus
  12. K. Usami and N. Ohkubo, “A design approach for fine-grained run-time power gating using locally extracted sleep signals,” in Proceedings of the 24th International Conference on Computer Design (ICCD '06), pp. 155–161, October 2006. View at Publisher · View at Google Scholar · View at Scopus
  13. T. Handa, Y. Yoshimoto, K. Nakayama, and A. Kitagawa, “Novel power reduction technique for ReRAM with automatic avoidance circuit for wasteful overwrite,” Active and Passive Electronic Components, vol. 2012, Article ID 181395, 11 pages, 2012. View at Publisher · View at Google Scholar