Single-Resistance-Controlled Sinusoidal Oscillator Using Single VD-DIBA

Abstract

This paper presents a new single-resistance-controlled sinusoidal oscillator (SRCO). The proposed oscillator employs only one voltage differencing differential input buffered amplifier (VD-DIBA), two resistors, and two grounded capacitors. The proposed configuration offers the following advantageous features: (i) independent control of condition of oscillation and frequency of oscillation, (ii) low active and passive sensitivities, and (iii) a very good frequency stability. The validity of the proposed SRCO has been established by SPICE simulations using 0.35 μm MIETEC technology.

1. Introduction

Realisation of oscillators and active filters has become important research area in analog circuit design. Recently, various modern active building blocks have been introduced in [1], and VD-DIBA is one of them which is emerging as a very flexible and versatile building block for analog signal processing and has been used earlier for realizing a number of functions. Single-resistance-controlled sinusoidal oscillators (SRCOs) play an important role in control systems, signal processing, communication, and instrumentation and measurement systems [2–4]. SRCOs employing different active building blocks have attracted considerable attention of the researchers due to their several advantages over traditional op-amp-based SRCOs; see [5–15] and the references cited therein. The applications, advantages, and usefulness of VD-DIBA have now been recognised in the realisation of first-order all-pass filter, in simulation of inductors and in the realisation of sinusoidal oscillator [16–18]. However, to the best of the knowledge and belief of the authors, none of the SRCOs using single VD-DIBA has yet been presented in the literature so far. Therefore, the purpose of this paper is to present a new SRCO using a single VD-DIBA along with a bare minimum number of four passive components. The proposed configuration offers (i) independent control of condition of oscillation and frequency of oscillation, (ii) low active and passive sensitivities, and (iii) a very good frequency stability. The workability of the proposed SRCO has been established by SPICE simulations using 0.35 μm MIETEC technology.

2. New Oscillator Configuration

The schematic symbol and behavioral model of the VD-DIBA are shown in Figures 1(a) and 1(b), respectively. The model includes two controlled sources: the current source controlled by differential voltage (𝑉₊−𝑉₋), with the transconductance 𝑔_𝑚, and the voltage source controlled by differential voltage (𝑉_𝑧−𝑉_𝑣), with the unity voltage gain. The VD-DIBA can be described by the following set of equations: 𝐼₊𝐼₋𝐼_𝑧𝐼_𝑣𝑉_𝑤=𝑔0000000000_𝑚−𝑔_𝑚𝑉00000000001−10⁺𝑉₋𝑉_𝑧𝑉_𝑣𝐼_𝑤. (1) A routine circuit analysis of Figure 2 yields the following characteristic equation: 𝑠²𝐶₁𝐶₂𝑅₁𝑅₂+𝑠𝑅₁2𝐶₁−𝐶₂𝑔_𝑚𝑅₂+1=0. (2) Thus, the condition of oscillation (CO) and frequency of oscillation (FO) are given by CO:2𝐶₁−𝐶₂𝑔_𝑚𝑅₂≤0,FO:𝑓₀=12𝜋1𝐶₁𝐶₂𝑅₁𝑅₂. (3)(4) Therefore, it is seen that FO is independently controllable by resistor 𝑅₁ and CO is controlled by 𝑔_𝑚.

(a)

(b)

Figure 1 

(a) Schematic symbol and (b) behavioural model of VD-DIBA.

Figure 2 

The proposed configuration.

3. Frequency Stability Analysis

Frequency stability may be considered to be an important figure of merit of an oscillator. The frequency stability factor is defined as 𝑆^𝐹=𝑑𝜙(𝑢)/𝑑𝑢, where 𝑢=𝜔/𝜔₀ is the normalized frequency, and 𝜙(𝑢) represents the phase function of the open loop transfer function of the oscillator circuit, with 𝐶₁=𝐶₂=𝐶,  𝑅₂=2𝑅,  𝑅=1/𝑔_𝑚, and 𝑅₁=𝑅/𝑛;  𝑆^𝐹 for the proposed SRCO is found to be 𝑆^𝐹=√2𝑛−2𝑛√2𝑛+1≈−2𝑛for𝑛≫1. (5) Thus, for larger values of 𝑛, the oscillator enjoys a very good frequency stability.

4. Nonideal Analysis and Sensitivity Performance

Let 𝑅_𝑍 and 𝐶_𝑍 denote the parasitic resistance and parasitic capacitance of the 𝑍-terminal of the VD-DIBA. Taking the nonidealities into account, namely, the voltage of  𝑊-terminal 𝑉_𝑊=(𝛽⁺𝑉_𝑍−𝛽⁻𝑉_𝑉), where 𝛽⁺=1−𝜀_𝑝  (𝜀_𝑝≪1) and 𝛽⁻=1−𝜀_𝑛  (𝜀_𝑛≪1) denote the voltage tracking errors of 𝑍-terminal and 𝑉-terminal of the VD-DIBA, respectively, then the expressions for CO and FO become CO:𝛽⁻+1𝐶₁+𝐶_𝑧−𝐶₂𝛽⁺𝑅−1²𝑅₁+𝛽⁺𝑔_𝑚𝑅₂+𝑅₂𝑅_𝑧≤0,FO:𝜔₀=𝛽⁺−𝛽⁻+1𝛽⁺−1+𝛽⁻+1𝑅₁/𝑅_𝑍𝐶₁+𝐶_𝑍𝐶₂𝑅₁𝑅₂. (6)(7) The left-hand side of (3) with the component values shown in Section 4 turns out to be −0.812 which is in accordance with (3) (<0). On the other hand, when left-hand side of (6) is calculated using the components and parasitic values in Section 4, it turns out to be −0.7992. It is therefore seen that both values are quite close from these numerical examples; it can be inferred that by considering 𝐶₁≫𝐶_𝑍, and   𝑅₁, 𝑅₂≪𝑅_𝑍, (6) becomes {2𝐶₁−𝐶₂𝑅₂(𝑔_𝑚+1/𝑅_𝑧)}≤0 which shows that (6) is almost the same as (3).

Its active and passive sensitivities can be found as 𝑆^𝜔0_𝐶11=−2𝐶₁𝐶₁+𝐶_𝑍,𝑆^𝜔0_𝐶21=−2,𝑆^𝜔0_𝐶𝑍1=−2𝐶_𝑍𝐶₁+𝐶_𝑍,𝑆^𝜔0_𝑅11=−21+𝛽⁻+1𝑅₁/𝑅_𝑍/𝛽⁺−𝛽⁻+1𝛽⁺,𝑆−1_𝜔0𝑅21=−2,𝑆^𝜔0_𝑅𝑍1=−2𝑅_𝑍𝛽⁻+1𝑅₁𝛽⁺−𝛽⁻+1𝛽⁺−1+𝛽⁻+1𝑅₁,𝑆^𝜔0_𝛽+=12𝛽⁺𝛽⁻+1𝑅₁/𝑅_𝑍−𝛽⁻1+𝛽⁺−1𝑅₁/𝑅_𝑍−𝛽⁻,𝑆^𝜔0_𝛽−=12𝛽⁻𝑅₁/𝑅_𝑍−𝛽⁺−11+𝛽⁺−1𝑅₁/𝑅_𝑍−𝛽⁻. (8)(9) In the ideal case, the various sensitivities of FO with respect to 𝑅₁,  𝑅₂,  𝐶₁, and 𝐶₂ are found to be 𝑆^𝜔0_𝑅1=𝑆^𝜔0_𝑅2=𝑆^𝜔0_𝐶1=𝑆^𝜔0_𝐶21=−2. (10) Considering the typical values of various parasitic, for example, 𝐶_𝑧=0.81 pF, 𝑅_𝑧=53 kΩ, and 𝛽⁺=𝛽⁻=1 along with 𝐶₁=𝐶₂=0.01 nF,  𝑅₁=1 kΩ, and 𝑅₂=9.5 kΩ, the various sensitivities are found to be  𝑆^𝜔0_𝐶1=−0.4625,  𝑆^𝜔0_𝐶2=−0.5,  𝑆^𝜔0_𝐶𝑍=−0.03747,  𝑆^𝜔0_𝑅1=−0.3681,  𝑆^𝜔0_𝑅2=−0.5, 𝑆^𝜔0_𝑅𝑍=−0.132,  𝑆^𝜔0_𝛽+=−0.17925, and  𝑆^𝜔0_𝛽−=0.0896  which are all low.

5. Simulation Results

To confirm theoretical analysis, the proposed SRCO was simulated using CMOS VD-DIBA (as shown in Figure 3). The passive elements were selected as 𝐶₁=𝐶₂=0.01 nF, 𝑅₁=1 KΩ, and 𝑅₂=9.5 KΩ. The transconductance of VD-DIBA was controlled by bias voltage 𝑉_B1. PSPICE-generated output waveforms indicating transient and steady state responses are shown in Figures 4(a) and 4(b), respectively. These results, thus, confirm the validity of the proposed configuration. Figure 5 shows the output spectrum, where the total harmonic distortion (THD) is found to be 2.77%. Figure 6 shows the variation of frequency with resistance 𝑅₁. A comparison with other previously known SRCOs using different active building blocks has been given in Table 2.

Figure 3 

Proposed CMOS implementation of VD-DIBA; 𝑉DD=−𝑉SS=2 V,  𝑉B1=−0.44 V, 𝑉B2=𝑉B3=−0.22  V, and 𝑉B4=−0.9  V.

(a)

(b)

Figure 4 

(a) Transient output waveform. (b) Steady state response of the output.

Figure 5 

Simulation result of the output spectrum.

Figure 6 

Variation of frequency with resistance 𝑅1.

The CMOS VD-DIBA is implemented using 0.35 μm MIETEC real transistor model which is listed in Box 1.

Box 1 

Aspect ratios of transistors used in Figure 3 are given in Table 1.

Table 1 

Table 2 

6. Conclusions

A new application of a recently introduced VD-DIBA in the realisation of SRCO has been proposed. The proposed configuration employs a minimum possible number of passive elements (namely, two resistors and two grounded capacitors) and yet offers independent control of FO through the resistor 𝑅₁ and CO through the transconductance 𝑔_𝑚 (hence, the circuit enjoys the electronic control of CO), low active and passive sensitivities, and a very good frequency stability. This paper thus added a new application circuit to the existing repertoire of VD-DIBA-based application circuits.