Research Article
Usage and Limitation of Standard Mobility Models for TCAD Simulation of Nanoscaled FD-SOI MOSFETs
Table 1
Process parameters for deposited layers of fabricated devices.
| Layer # | Layer name | Layer acronym | Layer thickness [nm] | Function and properties |
| 01 | Bulk silicon | Bulk | 500,000 | Substrate p-type boron (1015 cm−3) Resistivity: 14–22 Ω·cm Orientation |
| 02 | Buried oxide | BOX | 70 | Bulk insulator O+ implantation energy: 120 keV (2.35 hours) Dose: 0.39 1018 O+cm−2 Annealing: 1320°C (6.00 hours) |
| 03a | Silicon-On-Insulator | SOI | 46 | p-type boron (1015 cm−3) regular transistor channel in UTB devices and nonreduced SOI in GRC devices (source-drain extensions) |
| 03b | Gate-recessed silicon | GRS | 1.6–6.5 range | Thinned transistor channel in GRC devices |
| 03c | Pad oxide | PAD OX | 15 | Relieve stress from silicon to nitride at high temperature |
| 04 | Gate oxide | GOX | 26 | Gate insulator |
| 05 | Polysilicon | Poly | 220 | Gate electrode |
| 06 | Nitride 2 | Nit | 30 | Prevent further oxidation of the thin silicon layer during the implant's thermal annealing (GRC) |
| 07 | Field oxide | FOX | 700 | Active area insulator |
| 08 | Silox | SOX | 350 | Contact opening mask for source/drain and gate passivation |
| 09 | Polysilicon | Poly | 220 | Source/drain poly contacts Source/drain doping obtained by phosphorous implant: dose = 2.5 1015 cm−2, energy = 30 keV, HTA high temperature annealing = 1000°C, (30 min) |
| 10 | Aluminum | Al | 500 | Source/drain metal contacts |
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