Comprehensive Optimization of Dual Threshold Independent-Gate FinFET and SRAM Cells

Table 1

Comparison with previous works.

	Ref. [2]	Ref. [3]	Ref. [4]	This work
L	32nm	25nm	22nm	14nm
Hfin	40nm	1um	1um	40nm
	undoped	1e16	10e15	1e12
	2e20	N/A	10e20	1e20
TSI	H:6nm; L:12nm	H:9nm; L:N/A	H:80nm; L:80nm	H:6nm; L:6nm
EOT	L:1nm; H:2nm	H:1nm; L:N/A	H:2nm; L:2nm	H:0.75nm; L:0.8nm
GWF	H:4.8; L:4.5	H:4.85; L:N/A	H:5.2; L:4.5	H:4.9; L:4.55
Gate	Poly	MGHK	MGHK	MGHK
Vdd	0.9V	0.6V	1V	0.6V
Id10	H:1.0e-9A,; L:2.0e-5A	H: 4.0e-7A; L:N/A	H:2.0e-8A; L:1.0e-3A	H:2.0e-9A; L: 7.7e-6A
Id11	H:1.0e-5A; L:4.0e-5A	H: 1.0e-4A; L:N/A	H:1.0e-4A; L:2.0e-3A	H:2.4e-6A; L:3.2e-5A
	H:5.0e-12A; L:2.0e-11A	H: 2.0e-13A; L:N/A	H:2.0e-15A; L:2.0e-9	H:6.6e-13A; L: 1.6e-8A
	H: 2.0e+6; L2.0e+6	H:5.0e+6; L: N/A	H: 5.0e+10; L: 1.0e+6	H: 3.6e+6; L: 2.0e+3
Opt.; Tools	FUDG/TCAD	MEDICI	MEDICI	Sentaurus Device

H: high-Vth transitor; L: low-Vth transistor.