Abstract
TCAD tools have been largely improved in the last decades in order to support both process and device complementary simulations which are usually based on continuously developed models following the technology progress. In this paper, we compare between experimental and TCAD simulated results of two kinds of nanoscale devices: ultrathin body (UTB) and nanoscale Body (NSB) SOI-MOSFET devices, sharing the same W/L ratio but having a channel thickness ratio of 10 : 1 (46 nm and 4.6 nm, resp.). The experimental transfer I-V characteristics were found to be surprisingly different by several orders of magnitude. We analyzed this result by considering the severe mobility degradation and the influence of a large gate voltage dependent series resistance (). TCAD tools do not usually consider to be either channel thickness or gate voltage dependent. After observing a clear discrepancy between the mobility values extracted from our measurements and those modeled by the available TCAD models, we propose a new semiempirical approach to model the transfer characteristics.
1. Introduction
Nanoscale silicon-on-insulator (SOI) metal-oxide-semiconductor field-effect transistor (MOSFET) based devices are the building blocks of up-to-date systems allowing ultrafast data processing. This is in accordance with efforts to develop new generation of ultrafast computers based on combined electronic and signal processing on one hand [1] and advanced generations of nanoscale devices (NSB) for communication systems [2] on the other hand. Furthermore, the excellent control of leakage current and short channel effects, achievable by means of UTB SOI-MOSFET architectures, makes them good candidates for ultimate nanometer scale. Consequently, the transport properties’ study of thin semiconductor films has attracted considerable attention in the recent years.
In this perspective, the use of TCAD tools for predicting and optimizing such advanced semiconductor devices has increased recently [3, 4]. Since the nanotechnology’s process and device evolution is quite rapid, there may appear some gaps among existing TCAD models. Indeed, TCAD tools use classic parametric models where some of them tend to become obsolete for nanoscale devices. For instance, it is well established that quantum effects and/or interface effects mainly govern the conduction of modern devices (e.g., ballistic transport effects or decreasing of the mobility by decreasing the channel thickness) [5]. Moreover, series resistance effects are of great importance for such devices and are the scope of intensive research activities [6–8] as well as the usage of the Y-function method in the last decades [9–12] to extract this parameter [13]. In this paper, we show how a semiempirical model based on gate voltage dependent series resistance established in a previous work [8] can be integrated in a TCAD simulator to match nonconventional electrical transfer characteristics of FD-SOI MOSFETs.
2. TCAD Process Simulation
The layers deposition process was simulated by a commercial 3D TCAD process simulator (Csuprem from Crosslight) according to the process conditions used to fabricate the devices as previously published [8]. In Figures 1(a) and 1(b) we present the simulated 3D structure of the ultrathin body (UTB) device, having a 46 nm thick body and channel and ratio of 10 (80 μm/8 μm) and used as a reference device. In Figures 2(a) and 2(b), we show the simulated 3D structure of a ten-time reduced 4.6 nm thick channel obtained by the gate-recessed process, that is, the nanoscale body (NSB) device, sharing the same and values. As presented in Figures 1(a) and 2(a), the active region (source, gate, and drain terminals) is terminated by aluminum contacts (layer 10) in the vertical axis and limited by field oxide (layer 07) borders in the horizontal axis. The buried oxide (layer 02) is serving as a barrier between the bulk silicon (layer 01) and the gate-recessed silicon channel (layer 03).
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(b)
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Figure 2(b) represents a zoom-in of the gate-recessed channel, when the silicon layer was thinned from 46 nm to 4.6 nm. This points out advantage of the recessed process in which only the silicon channel is thinned while the source and drain regions and their respective extensions are remaining in their original (body) thickness. So the series resistance of the drain and of the source should not be affected a priori by the thinning process [14].
In addition to Figures 1 and 2, presenting a simulated TCAD cross-view of the device layers, a complementary list of the process parameters, most of which are used in the simulator, was presented in summarizing Table 1. Both the NSB and UTB devices were modeled in TCAD by applying almost the same process parameters used in their physical fabrications. However, the NSB process deviated from its actual microfabrication in the timing of annealing steps. Due to quite difficult control of the channel doping and thus of the threshold voltage in NSB devices, only a single annealing step was applied after ion implantation for a very short period (1-2 min, 1000°C) to fit the measured threshold voltage. It was observed that a slight change in the annealing time in the simulation could be enough to convert the channel region into excessively doped silicon due to the donors’ diffusion from the drain and source sides. Furthermore, since dry oxidation of polysilicon is not available in the used simulation tool, a deposition (plus annealing for 46 nm) step was inserted.
3. Electrical Transfer Characteristics
3.1. Measurements versus Simulations
measurements (room temperature and dark conditions) were performed on both the UTB and the NSB’s devices having a common channel width and length ( = 80 μm/8 μm = 10) but a channel thickness of 46 nm and 4.6 nm, respectively. The corresponding transfer characteristics, that is, drain currents () versus gate voltage () from −2 to +2 V, were measured in the linear domain (constant low V) and are presented in Figure 3. In addition we added the corresponding simulated characteristics (Apsys from Crosslight) using the default Canali or the so-called “beta” model [15] for the electron mobility as described in the next paragraph.
By increasing from −2 V to about −1 V, slowly decreases, indicating a leakage phenomenon similar to the Gate Induced Drain Leakage (GIDL) observed for both classic and SOI-MOSFET devices [16]. The phenomenon is ignored in the simulation.
For varying from −1 V to −0.5 V, the observed increasing steep is related to the subthreshold regime. We note that the subthreshold slope is strongly degraded by decreasing the channel thickness and may be due to a poor interface quality and/or a parasitic gate capacitance induced by the gate-recessed process. In the transfer curve, the threshold voltage () can be defined as the gate voltage for which the exponential extrapolation of subthreshold current deviates by 10% from the measured current [17]. This can be visualized by the highest point of the linear behavior in the semilog graph representation as shown in Figure 3. We preferred extracting from the weak inversion region, since we argued that the strong inversion region, from which the value is generally extracted, is already overwhelmed by the series resistance, for NSB device.
We note that the measured value for NSB (−0.8 V) is lower than UTB’s one (−0.4 V). However, for UTB’s devices thinner than 10 nm typically, VT is expected to increase by thinning the channel due to quantum effects as reported [18]. So, in our case, the lowering could be rather related to a degradation of quality gate oxide that may occur during the thinning process.
3.2. Extraction of Field Dependent Mobility: Default Model versus Measurement
The TCAD device simulator (Apsys from Crosslight) uses a default field dependent mobility model, the so-called “beta” model [15], as described below for electron carrier: where is the low field electron mobility, is the electrical field, is the electron velocity saturation, and is an exponent parameter (fixed to one as a default value).
The beta model in (1) was used as an initial guess model with its defaults values. However, in order to have a better agreement with experimental result, an additional mobility reduction factor of 0.728 was used for the UTB device. This factor is reasonable since the electron mobility in SOI film is expected to be lower than in the bulk. Afterwards, the same electrical simulation without the reduction factor was simulated on the 4.6 nm thick NSB device. The simulation results are presented in Figure 3.
Since is fixed to 0.1 V, we can extract an a priori effective channel electron mobility using the following linear expression of the measured drain current:
This expression allows also extracting the mobility dependence of the electron mobility from the TCAD simulations.
Figure 4 shows the dependence of the electron mobility relative to , as extracted from (2) for the NSB device and compared to UTB used for reference. We can notice a large and unexpected discrepancy between the mobility values extracted from simulation and measurement for NSB. In order to get a match for the NSB device, an outstanding reduction factor of 0.042 should be used in contrast to the 0.728 factor used for UTB. Consequently, unlike UTB, the default beta model has failed to reproduce our experimental results for NSB. Note that the split technique, usually employed for mobility extraction, was examined in a previous study [8]. But, we found out that a large series resistance can deteriorate the characteristics consistently with our experimental results so the channel mobility cannot be discriminated by this technique for such NSB devices.
4. Methodology for TCAD Simulations of the NSB Transfer Characteristics
4.1. Limits of TCAD Standard Simulation Models
As a first approach, the transfer characteristics of the devices were simulated by existing mobility models which are available in the TCAD toolbox.
In Figure 5, a fitting of the mobility between the simulated NSB device and experimental result was presented. Using the same default beta model given in (1) and by introducing a prefactor of 0.042, obtained from the ratio between the simulated mobility and measured mobility values of the NSB device (see Figure 4), it is possible to get good agreement with the experimental result of the 4.6 nm device for gate voltages below −0.5 V (beta modified mobility curve). Above −0.5 V, the characteristics start to deviate from the experimental data indicating a discrepancy of the beta model. It is important to note that a prefactor was preferably used instead of manipulating the model parameters and in (1).
Other existing models of mobility reduction, due to transverse field (perpendicular to the MOSFET channel), have been implemented as follows and plotted in Figure 5.(1)The model “Intel1” based on pisces-2ET manual (Stanford University) [19] defines a factor to reduce the mobility under the channel:where is the field perpendicular to the SiO2/Si interface and is bulk mobility value for electron in silicon at 300 K (1500 cm2·V−1·s−1). and β are the critical field and the exponent factor, respectively, indicated in Table 2.(2)The model “Intel2” also based on pisces-2ET manual (Stanford University) defines another kind of factor to reduce the mobility under the channel according to the so-called “universal mobility curve” as follows: (3)A more refined model called Lombardi’s model [20] proposes to integrate the contributions to mobility from different mechanisms as follows:where is this time of the mobility due to longitudinal field/hot-carrier effect. The other terms are due to acoustic phonons and surface roughness defined, respectively, bywhere , , and are, respectively, the lattice temperature, velocity equivalent factor, and the average doping concentration (1017 cm−3). At room temperature, for very thin channel, the surface roughness is the dominant back-scattering mechanism (see [1, chapter 7]). So we only modified the δ parameter of the component in Lombardi’s model.
The mentioned models were modified to fit the NSB experimental characteristics till getting a nonphysical behavior (i.e., null transconductance, except the beta model). The corresponding parameters are shown in Table 2.
The transfer characteristics simulated using all the above models (default and modified) are added in Figure 5 for NSB device. However, except the beta model, the modified models are still presenting a discrepancy of more than one order of magnitude compared to the measurement. But even in the modified beta model the prefactor should be changed by a small factor leading to very low electron mobility for such kind of devices (less than 10 cm2 V−1 s−1). These results lead us to insert the series resistance influence in the transport model of the NSB device.
4.2. Application of versus Model to NSB Device
In order to describe the NSB measured transfer characteristic by the influence of a series resistance, we used the gate voltage and body thickness dependent series resistance model, presented in [8] which is considered as the access resistance . Consider with MΩ, = 1.03 nm, and nmV−1.
A resistance extraction was made for = 4.6 nm and gate voltages between −0.5 and 2 V and shown in Figure 6.
4.3. Influence of on the Simulated Transfer Characteristics
The was simulated using the field dependent beta model without the reduction mobility factor of 0.042. The series resistance can be included in the TCAD device simulator as an external lumped element but for a fixed value of . Thus we simulated characteristics for each extracted resistance values in the range of −0.5 V to 2 V with 0.5 V steps (six different values according to Figure 6). The influence of the voltage dependence on can be simulated by a postprocessing of the above simulated characteristics which is shown in Figure 7. Indeed, for a given curve corresponding to a given for a particular , for example, −0.5 V, the current value is sampled at this particular voltage . The process is then repeated for each curve at the value corresponding to the next step value. The reconstructed characteristic from the sampled values is shown as the graph with triangle symbols in Figure 7.
In Figure 8, we compare our reconstructed characteristic from Figure 7 (now called ) to the measured one and to the simulated one from the beta model with the reduction mobility factor of 0.042 only . While the latter is higher than the measured characteristic, it appears that reconstructed one is now lower. Mobility reduction and series resistance effect are in competition to reduce the drain current but each of them is dominating in a particular range of values (below −0.5 V and above −0.5 V, resp.). Consequently we suggest unifying both simulated characteristics to simulate the final current according the following equation inspired from Matthiessen’s mobility-like law:
It was found that an exponent value of gave the best fit to the experimental characteristics, as it is presented in Figure 8.
5. Conclusion
Nanoscale SOI-MOSFET devices were fabricated using a selective recessed gate thinning process to get channel thicknesses scaling from 46 nm down to 4.6 nm. We show that the anomalous degradation of electrical characteristics of the latter can be modeled by a gate controlled series resistance rather than merely by a mobility model. Using TCAD tools, the devices’ transfer characteristics were simulated using the series resistance model combined with a factorized mobility model. Based on simulation results, it could be better understood that for low gate voltage the degraded electron mobility may be the dominant factor while at high gate voltage the series resistance becomes the dominant factor. Among various tested mobility models we have found out that the best fit is obtained when combining the modified beta mobility model with the gate voltage dependent series model. We suggest that this semiempirical modeling approach may be useful as a TCAD embedded tool to model the behavior of other nanodevices for which series resistance and/or mobility degradation is of a great concern.
Conflict of Interests
The authors have no conflict of interests associated with this paper.