Active and Passive Electronic Components http://www.hindawi.com The latest articles from Hindawi Publishing Corporation © 2014 , Hindawi Publishing Corporation . All rights reserved. Design of a 2 GHz Linear-in-dB Variable-Gain Amplifier with 80-dB Gain Range Thu, 17 Apr 2014 12:03:58 +0000 http://www.hindawi.com/journals/apec/2014/434189/ A broadband linear-in-dB variable-gain amplifier (VGA) circuit is implemented in 0.18 μm SiGe BiCMOS process. The VGA comprises two cascaded variable-gain core, in which a hybrid current-steering current gain cell is inserted in the Cherry-Hooper amplifier to maintain a broad bandwidth while covering a wide gain range. Postlayout simulation results confirm that the proposed circuit achieves a 2 GHz 3-dB bandwidth with wide linear-in-dB gain tuning range from −19 dB up to 61 dB. The amplifier offers a competitive gain bandwidth product of 2805 GHz at the maximum gain for a 110-GHz ft BiCMOS technology. The amplifier core consumes 31 mW from a 3.3 V supply and occupies active area of 280 μm by 140 μm. Zhengyu Sun and Yuepeng Yan Copyright © 2014 Zhengyu Sun and Yuepeng Yan. All rights reserved. Harmonic-Rejection Compact Bandpass Filter Using Defected Ground Structure for GPS Application Thu, 03 Apr 2014 08:17:23 +0000 http://www.hindawi.com/journals/apec/2014/436964/ A miniaturized bandpass filter (BPF) using defected ground structure (DGS) resonator with the characteristic of harmonic rejection is developed in this paper. The second and third harmonics of the proposed BPF are rejected by the characteristic of stepped-impedance DGS resonator. Moreover, open stubs are established so that two adjustable transmission zeros can independently be created to extend the stopband and improve the rejection level. Finally, a second-order BPF, centered at 1.62 GHz with a stopband extended up to 5.6 GHz and a rejection level better than 20 dB, is designed and implemented for GPS application. A good agreement between simulation and measurement verifies the validity of this design methodology. Haiwen Liu, Baoping Ren, Xiang Xiao, Zhichong Zhang, Shen Li, and Suping Peng Copyright © 2014 Haiwen Liu et al. All rights reserved. New Realizations of Single OTRA-Based Sinusoidal Oscillators Mon, 10 Mar 2014 09:48:35 +0000 http://www.hindawi.com/journals/apec/2014/938987/ This study proposes three new sinusoidal oscillators based on an operational transresistance amplifier (OTRA). Each of the proposed oscillator circuits consists of one OTRA combined with a few passive components. The first circuit is an OTRA-based minimum RC oscillator. The second circuit is capable of providing independent control on the condition of oscillation without affecting the oscillation frequency. The third circuit exhibits independent control of oscillation frequency through a capacitor. This study first introduces the OTRA and the related formulations of the proposed oscillator circuits, and then discusses the nonideal effects, sensitivity analyses, and frequency stability of the presented circuits. The proposed oscillators exhibit low sensitivities and good frequency stability. Because the presented circuits feature low impedance output, they can be connected directly to the next stage without cascading additional voltage buffers. HSPICE simulations and experimental results confirm the feasibility of the new oscillator circuits. Hung-Chun Chien Copyright © 2014 Hung-Chun Chien. All rights reserved. Signal Integrity Analysis in Carbon Nanotube Based Through-Silicon Via Sun, 02 Mar 2014 00:00:00 +0000 http://www.hindawi.com/journals/apec/2014/524107/ Development of a reliable 3D integrated system is largely dependent on the choice of filler materials used in through-silicon vias (TSVs). This research paper presents carbon nanotube (CNT) bundles as prospective filler materials for TSVs and provides an analysis of signal integrity for different single- (SWCNT), double- (DWCNT), and multi-walled CNT (MWCNT) bundle based TSVs. Depending on the physical configuration of a pair of TSVs, an equivalent electrical model is employed to analyze the in-phase and out-phase delays. It is observed that, using an MWCNT bundle (with number of shells = 10), the overall in-phase delays are reduced by 96.86%, 92.33%, 78.35%, and 32.72% compared to the bundled SWCNT, DWCNT, 4-shell MWCNT, and 8-shell MWCNT, respectively; similarly, the overall reduction in out-phase delay is 85.89%, 73.38%, 45.92%, and 12.56%, respectively. Manoj Kumar Majumder, Archana Kumari, Brajesh Kumar Kaushik, and Sanjeev Kumar Manhas Copyright © 2014 Manoj Kumar Majumder et al. All rights reserved. Bandwidth Extension of High Compliance Current Mirror by Using Compensation Methods Tue, 21 Jan 2014 00:00:00 +0000 http://www.hindawi.com/journals/apec/2014/274795/ Due to the huge demand of high-speed analog integrated circuits, it is essential to develop a wideband low input impedance current mirror that can be operated at low power supply. In this paper, a novel wideband low voltage high compliance current mirror using low voltage cascode current mirror (LVCCM) as a basic building block is proposed. The resistive compensation and inductive peaking methods have been used to extend the bandwidth of the conventional current mirror. By replacing conventional LVCCM in a high compliance current mirror with the compensated LVCCM, the bandwidth extension ratio of 3.4 has been achieved with no additional DC power dissipation and without affecting its other performances. The circuits are designed in TSMC 0.18 μm CMOS technology on Spectre simulator of Cadence. Maneesha Gupta, Urvashi Singh, and Richa Srivastava Copyright © 2014 Maneesha Gupta et al. All rights reserved. Three Microwave Frequency Dividers Using Current Source/Sink and Modified Current Source Inverters Mon, 30 Dec 2013 10:27:30 +0000 http://www.hindawi.com/journals/apec/2013/762706/ In a preceding paper Carlos E. Saavedra, 2005, established that frequency division can be achieved with the use of inverter rings and transmission gates. In this paper, we suggest three modified circuits which obtain the similar function, namely, using Current Sink Inverter, Current Source Inverter, and Modified Current Source Inverter. The performances of the proposed circuits are examined using Cadence and the model parameters of a 45 nm CMOS process. The simulation results of the three circuits are presented and are compared. We also present the results of a simple but effective novel technique to reduce clock skew between real and complementary clock signals and the corresponding improvement achieved in maximum frequency of operation. One of the proposed circuits can operate at up to 8.2 GHz input while performing a divide-by-4 operation. Gautham S. Harinarayan and Avireni Srinivasulu Copyright © 2013 Gautham S. Harinarayan and Avireni Srinivasulu. All rights reserved. A Low-Power Ultrawideband Low-Noise Amplifier in 0.18 μm CMOS Technology Tue, 24 Dec 2013 14:47:16 +0000 http://www.hindawi.com/journals/apec/2013/953498/ This paper presents an ultrawideband low-noise amplifier chip using TSMC 0.18 μm CMOS technology. We propose a UWB low noise amplifier (LNA) for low-voltage and low-power application. The present UWB LNA leads to a better performance in terms of isolation, chip size, and power consumption for low supply voltage. This UWB LNA is designed based on a current-reused topology, and a simplified RLC circuit is used to achieve the input broadband matching. Output impedance introduces the LC matching method to reduce power consumption. The measured results of the proposed LNA show an average power gain (S21) of 9 dB with the 3 dB band from 3 to 5.6 GHz. The input reflection coefficient (S11) less than −9 dB is from 3 to 11 GHz. The output reflection coefficient (S22) less than −8 dB is from 3 to 7.5 GHz. The noise figure 4.6–5.3 dB is from 3 to 5.6 GHz. Input third-order-intercept point (IIP3) of 2 dBm is at 5.3 GHz. The dc power consumption of this LNA is 9 mW under the supply of a 1 V supply voltage. The chip size of the CMOS UWB LNA is  mm2 in total. Jun-Da Chen Copyright © 2013 Jun-Da Chen. All rights reserved. Circuit Implementation, Operation, and Simulation of Multivalued Nonvolatile Static Random Access Memory Using a Resistivity Change Device Sat, 14 Dec 2013 10:16:54 +0000 http://www.hindawi.com/journals/apec/2013/839198/ We proposed and computationally analyzed a multivalued, nonvolatile SRAM using a ReRAM. Two reference resistors and a programmable resistor are connected to the storage nodes of a standard SRAM cell. The proposed 9T3R MNV-SRAM cell can store 2 bits of memory. In the storing operation, the recall operation and the successive decision operation of whether or not write pulse is required can be performed simultaneously. Therefore, the duration of the decision operation and the circuit are not required when using the proposed scheme. In order to realize a stable recall operation, a certain current (or voltage) is applied to the cell before the power supply is turned on. To investigate the process variation tolerance and the accuracy of programmed resistance, we simulated the effect of variations in the width of the transistor of the proposed MNV-SRAM cell, the resistance of the programmable resistor, and the power supply voltage with 180 nm 3.3 V CMOS HSPICE device models. Kazuya Nakayama and Akio Kitagawa Copyright © 2013 Kazuya Nakayama and Akio Kitagawa. All rights reserved. Influence of Series Massive Resistance on Capacitance and Conductance Characteristics in Gate-Recessed Nanoscale SOI MOSFETs Wed, 11 Dec 2013 14:29:03 +0000 http://www.hindawi.com/journals/apec/2013/813518/ Ultrathin body (UTB) and nanoscale body (NSB) SOI MOSFET devices, having a channel thickness ranging from 46 nm (UTB scale) down to 1.6 nm (NSB scale), were fabricated using a selective “gate recessed” process on the same silicon wafer. The gate-to-channel capacitance and conductance complementary characteristics, measured for NSB devices, were found to be radically different from those measured for UTBS. Consistent and trends are observed by varying the frequency , the channel length , and the channel thickness (). In this paper, we show that these trends can be analytically modeled by a massive series resistance depending on the gate voltage and on the channel thickness. The effects of leakage conductance and interface trap density are also modeled. This modeling approach may be useful to analyze and/or simulate electrical behavior of nanodevices in which series resistance is of a great concern. Avraham Karsenty and Avraham Chelly Copyright © 2013 Avraham Karsenty and Avraham Chelly. All rights reserved. A 0.8–6 GHz Wideband Receiver Front-End for Software-Defined Radio Mon, 09 Dec 2013 16:08:18 +0000 http://www.hindawi.com/journals/apec/2013/725075/ A wideband (0.8–6 GHz) receiver front-end (RFE) utilizing a shunt resistive feedback low-noise amplifier (LNA) and a micromixer is realized in 90 nm CMOS technology for software-defined radio (SDR) applications. With the shunt resistive feedback and series inductive peaking, the proposed LNA is able to achieve a wideband frequency response in input matching, power gain and noise figure (NF). A micromixer down converts the radio signal and performs single-to-differential transition. Measurements show the conversion gain higher than 17 dB and input matching (S11) better than −7.3 dB from 0.8 to 6 GHz. The IIP3 ranges from −7 to −10 dBm, and the NF from 4.5 to 5.9 dB. This wideband receiver occupies 0.48 mm2 and consumes 13 mW. Kuan-Ting Lin, Tao Wang, and Shey-Shi Lu Copyright © 2013 Kuan-Ting Lin et al. All rights reserved. MCML D-Latch Using Triple-Tail Cells: Analysis and Design Mon, 04 Nov 2013 14:33:56 +0000 http://www.hindawi.com/journals/apec/2013/217674/ A new low-voltage MOS current mode logic (MCML) topology for D-latch is proposed. The new topology employs a triple-tail cell to lower the supply voltage requirement in comparison to traditional MCML D-latch. The design of the proposed MCML D-latch is carried out through analytical modeling of its static parameters. The delay is expressed in terms of the bias current and the voltage swing so that it can be traded off with the power consumption. The proposed low-voltage MCML D-latch is analyzed for the two design cases, namely, high-speed and power-efficient, and the performance is compared with the traditional MCML D-latch for each design case. The theoretical propositions are validated through extensive SPICE simulations using TSMC 0.18 µm CMOS technology parameters. Kirti Gupta, Neeta Pandey, and Maneesha Gupta Copyright © 2013 Kirti Gupta et al. All rights reserved. A Design of a Terahertz Microstrip Bandstop Filter with Defected Ground Structure Wed, 30 Oct 2013 10:26:02 +0000 http://www.hindawi.com/journals/apec/2013/192018/ A planar microstrip terahertz (THz) bandstop filter has been proposed with defected ground structure with high insertion loss (S21) in a stopband of −25.8 dB at 1.436 THz. The parameters of the circuit model have been extracted from the EM simulation results. A dielectric substrate of Benzocyclobutene (BCB) is used to realize a compact bandstop filter using modified hexagonal dumbbell-shape defected ground structure (DB-DGS). In this paper, a defected ground structure topology is used in a λ/4, 50 Ω microstrip line at THz frequency range for compactness. No article has been reported on the microstrip line at terahertz frequency regime using DGS topology. The proposed filter can be used for sensing and detection in biomedical instruments in DNA testing. All the simulations/cosimulations are carried out using a full-wave EM simulator CST V.9 Microwave Studio, HFSS V.10, and Agilent Design Suite (ADS). Arjun Kumar and M. V. Kartikeyan Copyright © 2013 Arjun Kumar and M. V. Kartikeyan. All rights reserved. A Novel Pseudo-PMOS Integrated ISFET Device for Water Quality Monitoring Wed, 02 Oct 2013 08:55:41 +0000 http://www.hindawi.com/journals/apec/2013/258970/ The paper presents a performance analysis of novel CMOS Integrated pseudo-PMOS ISFET (PP-ISFET) having zero static power dissipation. The main focus is on simulation of power and performance analysis along with the comparison with existing devices, which is used for water quality monitoring. The conventional devices, generally used, consume high power and are not stable for long term monitoring. The conventional device has the drawbacks of low value of slew rate, high power consumption, and nonlinear characteristics, but in this novel design, due to zero static power, less load capacitance on input signals, faster switching, fewer transistors, and higher circuit density, the device exhibits a better slew rate and piecewise linear characteristics and is seen consuming low power of the order of 30 mW. The proposed circuit reduces total power consumption per cycle, increases the speed of operation, is fairly linear, and is simple to implement. Pawan Whig and Syed Naseem Ahmad Copyright © 2013 Pawan Whig and Syed Naseem Ahmad. All rights reserved. Additional High Input Low Output Impedance Analog Networks Thu, 26 Sep 2013 18:06:01 +0000 http://www.hindawi.com/journals/apec/2013/574925/ This paper presents some additional high input low output impedance analog networks realized using a recently introduced single Dual-X Current Conveyor with buffered output. The new circuits encompass several all-pass sections of first- and second-order. The voltage-mode proposals benefit from high input impedance and low output impedance. Nonideality and sensitivity analysis is also performed. The circuit performances are depicted through PSPICE simulations, which show good agreement with theory. Sudhanshu Maheshwari and Bhartendu Chaturvedi Copyright © 2013 Sudhanshu Maheshwari and Bhartendu Chaturvedi. All rights reserved. Potential and Quantum Threshold Voltage Modeling of Gate-All-Around Nanowire MOSFETs Thu, 19 Sep 2013 14:32:02 +0000 http://www.hindawi.com/journals/apec/2013/153157/ An improved physics-based compact model for a symmetrically biased gate-all-around (GAA) silicon nanowire transistor is proposed. Short channel effects and quantum mechanical effects caused by the ultrathin silicon devices are considered in modelling the threshold voltage. Device geometrics play a very important role in multigate devices, and hence their impact on the threshold voltage is also analyzed by varying the height and width of silicon channel. The inversion charge and electrical potential distribution along the channel are expressed in their closed forms. The proposed model shows excellent accuracy with TCAD simulations of the device in the weak inversion regime. M. Karthigai Pandian, N. B. Balamurugan, and A. Pricilla Copyright © 2013 M. Karthigai Pandian et al. All rights reserved. Current Mode Full-Wave Rectifier Based on a Single MZC-CDTA Thu, 18 Jul 2013 09:58:55 +0000 http://www.hindawi.com/journals/apec/2013/967057/ This paper presents a current mode full-wave rectifier based on single modified Z copy current difference transconductance amplifier (MZC-CDTA) and two switches. The circuit is simple and is suitable for IC implementation. The functionality of the circuit is verified with SPICE simulation using 0.35 μm TSMC CMOS technology parameters. Neeta Pandey and Rajeshwari Pandey Copyright © 2013 Neeta Pandey and Rajeshwari Pandey. All rights reserved. A Smart Infrared Microcontroller-Based Blind Guidance System Thu, 18 Jul 2013 08:41:18 +0000 http://www.hindawi.com/journals/apec/2013/726480/ Blindness is a state of lacking the visual perception due to physiological or neurological factors. The partial blindness represents the lack of integration in the growth of the optic nerve or visual centre of the eye, and total blindness is the full absence of the visual light perception. In this work, a simple, cheap, friendly user, smart blind guidance system is designed and implemented to improve the mobility of both blind and visually impaired people in a specific area. The proposed work includes a wearable equipment consists of head hat and mini hand stick to help the blind person to navigate alone safely and to avoid any obstacles that may be encountered, whether fixed or mobile, to prevent any possible accident. The main component of this system is the infrared sensor which is used to scan a predetermined area around blind by emitting-reflecting waves. The reflected signals received from the barrier objects are used as inputs to PIC microcontroller. The microcontroller is then used to determine the direction and distance of the objects around the blind. It also controls the peripheral components that alert the user about obstacle's shape, material, and direction. The implemented system is cheap, fast, and easy to use and an innovative affordable solution to blind and visually impaired people in third world countries. Amjed S. Al-Fahoum, Heba B. Al-Hmoud, and Ausaila A. Al-Fraihat Copyright © 2013 Amjed S. Al-Fahoum et al. All rights reserved. Single-Input Four-Output Current Mode Filter Using Operational Floating Current Conveyor Thu, 27 Jun 2013 09:07:49 +0000 http://www.hindawi.com/journals/apec/2013/318560/ This paper presents operational floating current conveyor (OFCC) based single input four output current mode filter. It employs only three OFCCs and two grounded capacitors and resistors each. The MOS based grounded resistors implementation is used, which adds feature of electronic tunability to the filter parameters. The filter also enjoys low component spread and low sensitivity performance. The effect of finite transimpedance and parasites of OFCC on the proposed circuit is also analyzed. The functionality of the proposed circuit is demonstrated through SPICE simulations using 0.5 µm CMOS process model provided by MOSIS (AGILENT). Neeta Pandey, Deva Nand, and Zubair Khan Copyright © 2013 Neeta Pandey et al. All rights reserved. Design and Analysis of Wideband Ladder-Type Film Bulk Acoustic Wave Resonator Filters in Ku-Band Sun, 23 Jun 2013 10:03:55 +0000 http://www.hindawi.com/journals/apec/2013/403516/ This paper presents the design of ladder-type filters based on film bulk acoustic wave resonator (FBAR) in Ku-band. The proposed FBAR filter has an insertion loss of −3 dB, out-of-band rejection of −12 dB and 3 dB bandwidth of 1.0 GHz from 15 GHz to 16 GHz. Based on the characteristics of the FBAR filter, the expected characteristics of FBAR resonators are determined by using the 1D numerical analysis. This design proves that it is possible to design a wide-bandwidth FBAR filter in Ku-band. N. Izza M. Nor, K. Shah, J. Singh, and Z. Sauli Copyright © 2013 N. Izza M. Nor et al. All rights reserved. Modeling of the Channel Thickness Influence on Electrical Characteristics and Series Resistance in Gate-Recessed Nanoscale SOI MOSFETs Sun, 02 Jun 2013 16:23:30 +0000 http://www.hindawi.com/journals/apec/2013/801634/ Ultrathin body (UTB) and nanoscale body (NSB) SOI-MOSFET devices, sharing a similar W/L but with a channel thickness of 46 nm and lower than 5 nm, respectively, were fabricated using a selective “gate-recessed” process on the same silicon wafer. Their current-voltage characteristics measured at room temperature were found to be surprisingly different by several orders of magnitude. We analyzed this result by considering the severe mobility degradation and the influence of a huge series resistance and found that the last one seems more coherent. Then the electrical characteristics of the NSB can be analytically derived by integrating a gate voltage-dependent drain source series resistance. In this paper, the influence of the channel thickness on the series resistance is reported for the first time. This influence is integrated to the analytical model in order to describe the trends of the saturation current with the channel thickness. This modeling approach may be useful to interpret anomalous electrical behavior of other nanodevices in which series resistance and/or mobility degradation is of a great concern. A. Karsenty and A. Chelly Copyright © 2013 A. Karsenty and A. Chelly. All rights reserved. Voltage-Mode Four-Phase Sinusoidal Generator and Its Useful Extensions Wed, 08 May 2013 17:28:21 +0000 http://www.hindawi.com/journals/apec/2013/685939/ This paper introduces a new voltage-mode second-order sinusoidal generator circuit with four active elements and six passive elements, including grounded capacitors. The frequency and condition of oscillation can be independently controlled. The effect of active element’s nonidealities and parasitic effects is also studied; the proposed topology is good in absorbing several parasitic elements involved with the active elements. The circuit is advantageous for generating high frequency signals which is demonstrated for 25 MHz outputs. Several circuit extensions are also given which makes the new proposal useful for real circuit adoption. The proposed theory is validated through simulation results. Sudhanshu Maheshwari Copyright © 2013 Sudhanshu Maheshwari. All rights reserved. Logic Gates and Ring Oscillators Based on Ambipolar Nanocrystalline-Silicon TFTs Mon, 29 Apr 2013 16:04:02 +0000 http://www.hindawi.com/journals/apec/2013/525017/ Nanocrystalline silicon (nc-Si) thin film transistors (TFTs) are well suited for circuit applications that require moderate device performance and low-temperature CMOS-compatible processing below 250°C. Basic logic gate circuits fabricated using ambipolar nc-Si TFTs alone are presented and shown to operate with correct outputs at frequencies of up to 100 kHz. Ring oscillators consisting of nc-Si TFT-based inverters are also shown to operate at above 20 kHz with a supply voltage of 5 V, corresponding to a propagation delay of <10 μs/stage. These are the fastest circuits formed out of nanocrystalline silicon TFTs to date. The effect of bias stress degradation of TFTs on oscillation frequency is also explored, and relatively stable operation is shown with supply voltages >5 V for several hours. Anand Subramaniam, Kurtis D. Cantley, and Eric M. Vogel Copyright © 2013 Anand Subramaniam et al. All rights reserved. Noise Performance of Heterojunction DDR MITATT Devices Based on at W-Band Sun, 28 Apr 2013 15:58:19 +0000 http://www.hindawi.com/journals/apec/2013/720191/ Noise performance of different structures of anisotype heterojunction double-drift region (DDR) mixed tunneling and avalanche transit time (MITATT) devices has been studied. The devices are designed for operation at millimeter-wave W-band frequencies. A simulation model has been developed to study the noise spectral density and noise measure of the device. Two different mole fractions and of Ge and corresponding four types of device structure are considered for the simulation. The results show that the -Si heterojunction DDR structure of MITATT device excels all other structures as regards noise spectral density ( sec) and noise measure (33.09 dB) as well as millimeter-wave properties such as DC-to-RF conversion efficiency (20.15%) and CW power output (773.29 mW). Suranjana Banerjee, Aritra Acharyya, and J. P. Banerjee Copyright © 2013 Suranjana Banerjee et al. All rights reserved. Single-Resistance-Controlled Sinusoidal Oscillator Using Single VD-DIBA Tue, 16 Apr 2013 11:24:31 +0000 http://www.hindawi.com/journals/apec/2013/971936/ This paper presents a new single-resistance-controlled sinusoidal oscillator (SRCO). The proposed oscillator employs only one voltage differencing differential input buffered amplifier (VD-DIBA), two resistors, and two grounded capacitors. The proposed configuration offers the following advantageous features: (i) independent control of condition of oscillation and frequency of oscillation, (ii) low active and passive sensitivities, and (iii) a very good frequency stability. The validity of the proposed SRCO has been established by SPICE simulations using 0.35 μm MIETEC technology. K. L. Pushkar, D. R. Bhaskar, and Dinesh Prasad Copyright © 2013 K. L. Pushkar et al. All rights reserved. A 0.8 V 0.23 nW 1.5 ns Full-Swing Pass-Transistor XOR Gate in 130 nm CMOS Sun, 31 Mar 2013 08:40:46 +0000 http://www.hindawi.com/journals/apec/2013/148518/ A power efficient circuit topology is proposed to implement a low-voltage CMOS 2-input pass-transistor XOR gate. This design aims to minimize power dissipation and reduce transistor count while at the same time reducing the propagation delay. The XOR gate utilizes six transistors to achieve a compact circuit design and was fabricated using the 130 nm IBM CMOS process. The performance of the XOR circuit was validated against other XOR gate designs through simulations using the same 130 nm CMOS process. The area of the core circuit is only about 56 sq · µm with 1.5659 ns propagation delay and 0.2312 nW power dissipation at 0.8 V supply voltage. The proposed six-transistor implementation thus compares favorably with other existing XOR gate designs. Nabihah Ahmad and Rezaul Hasan Copyright © 2013 Nabihah Ahmad and Rezaul Hasan. All rights reserved. Metal-Insulator-Semiconductor Field-Effect Transistors Thu, 07 Mar 2013 10:20:22 +0000 http://www.hindawi.com/journals/apec/2013/596065/ Kuan-Wei Lee, Edward Yi Chang, Yeong-Her Wang, Pei-Wen Li, and Yasuyuki Miyamoto Copyright © 2013 Kuan-Wei Lee et al. All rights reserved. A 60 GHz Planar Diplexer Based on Substrate Integrated Waveguide Technology Wed, 27 Feb 2013 08:16:06 +0000 http://www.hindawi.com/journals/apec/2013/948217/ This paper presents a millimeter-wave, 60 GHz frequency band planar diplexer based on substrate integrated waveguide (SIW) technology. Diplexer consists of a pair of 5th-order SIW bandpass channel filters with center frequencies at 59.8 GHz and 62.2 GHz providing 1.67% and 1.6% relative bandwidths, respectively. SIW-to-microstrip transitions at diplexer ports enable integration in a millimeter-wave transceiver front end. Measurements are in good agreement with electromagnetic simulation, reporting very good channel isolation, small return losses, and moderate insertion losses in the passbands. The proposed SIW planar diplexer is integrated into a millimeter-wave transceiver front end for 60 GHz point-to-point multigigabit wireless backhaul applications, providing high isolation between transmit and receive channels. Nikolaos Athanasopoulos, Dimitrios Makris, and Konstantinos Voudouris Copyright © 2013 Nikolaos Athanasopoulos et al. All rights reserved. A Novel Nanoscale FDSOI MOSFET with Block-Oxide Mon, 18 Feb 2013 17:17:07 +0000 http://www.hindawi.com/journals/apec/2013/627873/ We demonstrate improved device performance by applying oxide sidewall spacer technology to a block-oxide-enclosed Si body to create a fully depleted silicon-on-insulator (FDSOI) nMOSFET, which overcomes the need for a uniform ultrathin silicon film. The presence of block-oxide along the sidewalls of the Si body significantly reduces the influence of drain bias over the channel. The proposed FDSOI structure therefore outperforms conventional FDSOI with regard to its drain-induced barrier lowering (DIBL), on/off current ratio, subthreshold swing, and threshold voltage rolloff. The new FDSOI structure is in fact shown to behave similarly to an ultrathin body (UTB) SOI but without the associated disadvantages and technological challenges of the ultrathin film, because a thick Si body allows for reduced sensitivity to self-heating, thereby improving thermal stability. Jyi-Tsong Lin, Yi-Chuen Eng, and Po-Hsieh Lin Copyright © 2013 Jyi-Tsong Lin et al. All rights reserved. A Unified Channel Charges Expression for Analytic MOSFET Modeling Tue, 25 Dec 2012 10:48:05 +0000 http://www.hindawi.com/journals/apec/2012/652478/ Based on a 1D Poissons equation resolution, we present an analytic model of inversion charges allowing calculation of the drain current and transconductance in the Metal Oxide Semiconductor Field Effect Transistor. The drain current and transconductance are described by analytical functions including mobility corrections and short channel effects (CLM, DIBL). The comparison with the Pao-Sah integral shows excellent accuracy of the model in all inversion modes from strong to weak inversion in submicronics MOSFET. All calculations are encoded with a simple C program and give instantaneous results that provide an efficient tool for microelectronics users. Hugues Murray and Patrick Martin Copyright © 2012 Hugues Murray and Patrick Martin. All rights reserved. Comprehension of Postmetallization Annealed MOCVD- on Treated III-V Semiconductors Sun, 16 Dec 2012 08:38:50 +0000 http://www.hindawi.com/journals/apec/2012/148705/ The electrical characteristics of TiO2 films grown on III-V semiconductors (e.g., p-type InP and GaAs) by metal-organic chemical vapor deposition were studied. With (NH4)2S treatment, the electrical characteristics of MOS capacitors are improved due to the reduction of native oxides. The electrical characteristics can be further improved by the postmetallization annealing, which causes hydrogen atomic ion to passivate defects and the grain boundary of polycrystalline TiO2 films. For postmetallization annealed TiO2 on (NH4)2S treated InP MOS, the leakage current densities can reach and  A/cm2 at  MV/cm, respectively. The dielectric constant and effective oxide charges are 46 and  C/cm2, respectively. The interface state density is  cm−2 eV−1 at the energy of 0.67 eV from the edge of valence band. For postmetallization annealed TiO2 on (NH4)2S treated GaAs MOS, The leakage current densities can reach and at  MV/cm, respectively. The dielectric constant and effective oxide charges are 66 and  C/cm2, respectively. The interface state density is  cm−2 eV−1 at the energy of 0.7 eV from the edge of valence band. Ming-Kwei Lee and Chih-Feng Yen Copyright © 2012 Ming-Kwei Lee and Chih-Feng Yen. All rights reserved.