Recent Advances in Voltage References and Low-Dropout Regulators for System-on-Chip Applications
Call for Papers
The continual push for system-on-chip solutions in advanced nanometer CMOS technologies has posed serious challenges to the design of voltage references and low-dropout (LDO) regulators in power management. This is due to orders-of-magnitude increase in process leakage currents as well as wider variation in process parameters when compared to the conventional counterparts. It is very difficult to sustain the circuits operation to meet the robust design objective along with the temperature and supply variations. Such large PVT variations create an obstacle for precision or high-performance analog circuit design. In addition, with reduced supply environment, the design of the above blocks will be further pushed to another limit which may be difficult to meet the yield as well as to compromise the key performance parameters in a trade-off design solution. Advanced circuit techniques and/or methodologies will offer possible means to overcome or relax the stated problems arising from nanometer technologies. Therefore, we invite authors to submit original research or review articles that address the problems, issues, and design techniques of voltage references and LDO regulators for system-on-chip applications. Potential topics included but are not limited to:
- Voltage references
- Low-dropout regulators
- Mixed-mode low-dropout regulators
- Leakage/variation-aware voltage references/LDO regulators
- Low voltage/low-power voltage references/LDO regulators
- Frequency compensation techniques in LDO regulators
- PVT-insensitive current references for voltage references/LDO regulators
- Voltage references/LDO regulators for special applications
- Related power management techniques
Before submission authors should carefully read over the journal's Author Guidelines, which are located at http://www.hindawi.com/journals/apec/guidelines/. Prospective authors should submit an electronic copy of their complete manuscript through the journal Manuscript Tracking System at http://mts.hindawi.com/ according to the following timetable:
| Manuscript Due | Friday, 25 May 2012 |
| First Round of Reviews | Friday, 17 August 2012 |
| Publication Date | Friday, 12 October 2012 |
Lead Guest Editor
- Pak Kwong Chan, School of Electrical & Electronic Engineering, Nanyang Technological University, Singapore
Guest Editors
- Ka Nang Leung, Department of Electronic Engineering, Chinese University of Hong Kong, Shatin, New Territories, Hong Kong
- Chua Chin Wang, Department of Electrical Engineering, National Sun Yat-sen University, Kaohsiung, Taiwan