Design, Automation, and Test of Three-Dimensional Stacked ICs

Call for Papers

Three-dimensional (3D) integration using through-silicon via (TSV) is an emerging technology for integrated circuit design as it offers numerous opportunities for cost-effective system integration. By stacking dies vertically, the length of on-chip interconnect is reduced and the density between on-chip components is improved, offering potential to reduce power consumption and enhance performance, bandwidth, and throughput. In addition to homogeneous die stacking, 3D stacking enables heterogeneous integration of memories, logic, analog circuits, sensors, and so forth. which result in a smaller form factor. Nevertheless, the volume production of TSV-based 3D-SICs still faces several key challenges in areas such as process technology, yield and testability, power and thermal dissipation, and design methodology and tools. To facilitate the development of 3D-SICs, in this special issue, we invite original research articles as well as review articles that provide insights into the design automation and test of 3D-SICs. Potential topics include, but are not limited to:

• 3D-SIC design methods
• 3D-SIC electronic design automation
• Chip-package codesign for 3D-SICs
• Test and design-for-test for 3D-SICs
• 3D-SIC-specific KGD test
• Wafer test access for 3D-SICs
• Test optimization techniques for 3D-SICs
• Power or clock network synthesis for 3D-SICs
• Thermal analysis for 3D-SICs
• 3D-SIC debug techniques
• Standardization for 3D-SIC EDA and testing
• Cost modeling for 3D-SICs
• Yield learning for 3D-SICs
• Defect and fault modeling for 3D-SICs

Before submission authors should carefully read over the journal's Author Guidelines, which are located at http://www.hindawi.com/journals/apec/guidelines/. Prospective authors should submit an electronic copy of their complete manuscript through the journal Manuscript Tracking System at http://mts.hindawi.com/ according to the following timetable:

Lead Guest Editor

• Jin-Fu Li, Department of Electrical Engineering, National Central University, Jhongli, Taiwan

Guest Editors

• Hsien-Hsin S. Lee, School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA, USA
• Said Hamdioui, Department of Electrical Engineering, Mathematics and Computer Science, Delft University of Technology, Delft, The Netherlands
• Hsiu-Ming (Sherman) Chang, Logic Technology Development, Intel Corporation, Hillsboro, OR, USA