EURASIP Journal on Applied Signal Processing
Volume 2003 (2003), Issue 13, Pages 1306-1316
doi:10.1155/S1110865703309060
VLSI Design of a Variable-Length FFT/IFFT Processor for OFDM-Based Communication Systems
Graduate Institute of Electronics Engineering and Department of Electrical Engineering, National Taiwan University, Taipei 106, Taiwan
Received 30 January 2003; Revised 10 July 2003
Abstract
The technique of {orthogonal frequency division
multiplexing (OFDM)} is famous for its robustness against
frequency-selective fading channel. This technique has been
widely used in many wired and wireless communication systems. In
general, the {fast Fourier transform (FFT)} and {inverse FFT
(IFFT)} operations are used as the modulation/demodulation kernel
in the OFDM systems, and the sizes of FFT/IFFT operations are
varied in different applications of OFDM systems. In this paper,
we design and implement a variable-length prototype FFT/IFFT
processor to cover different specifications of OFDM applications.
The cached-memory FFT architecture is our suggested VLSI system
architecture to design the prototype FFT/IFFT processor for the
consideration of low-power consumption. We also implement the
twiddle factor butterfly {processing element (PE)} based on the
{{coordinate} rotation digital computer (CORDIC)} algorithm,
which avoids the use of conventional
multiplication-and-accumulation unit, but evaluates the
trigonometric functions using only add-and-shift operations.
Finally, we implement a variable-length prototype FFT/IFFT
processor with TSMC 0.35 μm 1P4M CMOS technology. The simulations results show that the chip can perform
(64-2048)-point FFT/IFFT operations up to 80 MHz operating frequency which can meet the speed requirement of most OFDM standards such as WLAN, ADSL, VDSL (256∼2K), DAB, and 2K-mode DVB.