EURASIP Journal on Applied Signal Processing
Volume 2005 (2005), Issue 7, Pages 1024-1034
doi:10.1155/ASP.2005.1024
FPGA-Based Configurable Systolic Architecture for Window-Based Image Processing
Computer Science Department, National Institute for Astrophysics, Optics and Electronics, P.O. Box 51 and 216, 72000, Puebla, Mexico
Received 13 September 2003; Revised 21 May 2004
Copyright © 2005 César Torres-Huitzil and Miguel Arias-Estrada. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.
Abstract
Image processing requires more computational power and data throughput than most conventional processors can provide. Designing specific hardware can improve execution time and achieve better performance per unit of silicon area. A field-programmable-gate-array- (FPGA-) based configurable systolic architecture specially tailored for real-time window-based image operations is presented in this paper. The architecture is based on a 2D systolic array of 7×7 configurable window processors. The architecture was implemented on an FPGA to execute algorithms with window sizes up to 7×7, but the design is scalable to cover larger window sizes if required. The architecture reaches a throughput of 3.16 GOPs at a 60 MHz clock frequency and a processing time of 8.35 milliseconds for 7×7 generic window-based operators on 512×512 gray-level images. The architecture compares favorably with other architectures in terms of performance and hardware utilization. Theoretical and experimental results are presented to demonstrate the architecture effectiveness.