EURASIP Journal on Applied Signal Processing
Volume 2005 (2005), Issue 7, Pages 1024-1034
doi:10.1155/ASP.2005.1024
FPGA-Based Configurable Systolic Architecture for Window-Based Image Processing
Computer Science Department, National Institute for Astrophysics, Optics and Electronics, P.O. Box 51 and 216, 72000, Puebla, Mexico
Received 13 September 2003; Revised 21 May 2004
Copyright © 2005 César Torres-Huitzil and Miguel Arias-Estrada. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.
How to Cite this Article
César Torres-Huitzil and Miguel Arias-Estrada, “FPGA-Based Configurable Systolic Architecture for Window-Based Image Processing,” EURASIP Journal on Applied Signal Processing, vol. 2005, no. 7, pp. 1024-1034, 2005. doi:10.1155/ASP.2005.1024