Quantization of VLSI Digital Signal Processing Systems

Call for Papers

Many modern DSP systems are implemented using custom hardware systems since they can cope with the ever-increasing demand for more and more complex multimedia and communications applications providing attractive form factors and energy consumption. After the design and validation of the DSP required for a given application, the so-called precision analysis or quantization is an unavoidable step of the hardware design process. The original infinite precision of the DSP algorithms must be reduced to the precision bounds imposed by practical digital computing systems. The quantization process aims at the selection of the word lengths of the variables of an algorithm to respect a certain accuracy constraint while optimizing the characteristics of the implementation (e.g., area, speed, power consumption, etc.). This process has a deep impact in the subsequent design tasks and, as a result, in the final produced system. Moreover, the quantization process is typically responsible of a significant share of design time of embedded DSP systems.

Quantization is not an easy task and in some cases it is oversimplified in order to meet the time-to-market constraints, leading to far from optimal results. However, in some other cases such a simplification is not possible without seriously compromising the viability of the system. As a result, an exhaustive quantization is carried out, implying the extensive use of time-consuming techniques such as computer simulations. Therefore, improvements in quantization error estimation techniques as well as novel methodologies able to handle industrial size systems within a reasonable design time are of crucial importance. In this special issue we encourage researchers to contribute with new techniques that allow reducing the design time cost without sacrificing the application performance and the overall system quality. Topics of interest include, but are not limited to:

• Automatic word-length optimization techniques
• Quantization noise estimation
• High-level computation of quantization effect on application performance
• Output noise constraint determination
• Quantization of complex DSP systems
• Novel hardware architectures for fixed-point/floating-point computation
• New arithmetic models: hybrid fixed-point/floating-point, and so forth
• Fixed-point versus floating-point systems
• Quantization of control systems
• Quantization for low power
• Quantization of custom floating-point algorithms
• Fixed-point/Floating-point filter design
• Combination with other design tasks: data-flow transformations, architectural mapping, floorplanning, routing, and so forth
• Reconfigurable devices: efficient use of logic fabric and DSP/RAM blocks, FPGA-specific quantization techniques, dynamic precision systems, and so forth

Before submission, authors should carefully read over the journal's Author Guidelines, which are located at http://www.hindawi.com/journals/asp/guidelines/. Prospective authors should submit an electronic copy of their complete manuscript through the journal Manuscript Tracking System at http://mts.hindawi.com/ according to the following timetable:

Lead Guest Editor

• Gabriel Caffarena, University of San Pablo-CEU, Madrid, Spain

Guest Editors

• Olivier Sentieys, INRIA, University of Rennes, Rennes, France
• Daniel Menard, INRIA, University of Rennes, Rennes, France
• Juan A. López, Technical University of Madrid (UPM), Madrid, Spain
• David Novo, IMEC vzw, Kapeldreef 75, 3001 Leuven, Belgium