Microcontroller Based Less Switches Topology and Digital Gating Technique for Single-Phase Five-Level Inverter

Figure 10

Experimental results: (a) implemented prototype setup, (b) and (c) gating for 𝑆₁ and 𝑆₄ signals, respectively, (d) output voltage for MI=0.8 and FMR=18, (e) output voltage for MI=0.8 and FMR=30, and (f) output voltage for MI=0.4 and FMR=18.

(a)

(b)

(c)

(d)

(e)

(f)