EURASIP Journal on Embedded Systems
Volume 2007 (2007), Article ID 54173, 14 pages
doi:10.1155/2007/54173
Research Article

Application-Specific Instruction Set Processor Implementation of List Sphere Detector

Juho Antikainen,1 Perttu Salmela,2 Olli Silvén,1 Markku Juntti,1 Jarmo Takala,2 and Markus Myllylä1

1Information Processing Laboratory and Centre for Wireless Communications, University of Oulu, Oulu 90014, Finland
2Institute of Digital and Computer Systems, Tampere University of Technology, Tampere 33101, Finland

Received 8 June 2007; Revised 18 October 2007; Accepted 12 November 2007

Academic Editor: Marco Platzner

Copyright © 2007 Juho Antikainen et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Abstract

Multiple-input multiple-output (MIMO) technology enables higher transmission capacity without additional frequency spectrum and is becoming a part of many wireless system standards. Sphere detection has been introduced in MIMO systems to achieve maximum likelihood (ML) or near-ML estimation with reduced complexity. This paper reviews related work on sphere detector implementations and presents an application-specific instruction set processor (ASIP) implementation of K-best list sphere detector (LSD) using transport triggered architecture (TTA). The implementation is based on using memory and heap data structure for symbol vector sorting. The design space is explored by presenting several variations of the implementation and comparing them with each other in terms of their latencies and hardware complexities. An early proposal for a parallelized architecture with a decoding throughput of approximately 5.3 Mbps is presented