EURASIP Journal on Embedded Systems
Volume 2007 (2007), Article ID 86273, 13 pages
doi:10.1155/2007/86273
Research Article
A Shared Memory Module for Asynchronous Arrays of Processors
Department of Electrical and Computer Engineering, University of California, Davis, CA 95616-5294, USA
Received 1 August 2006; Revised 20 December 2006; Accepted 1 March 2007
Academic Editor: Gang Qu
Copyright © 2007 Michael J. Meeuwsen et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.
Abstract
A shared memory module connecting multiple independently clocked
processors is presented. The memory module itself is independently clocked,
supports hardware address generation, mutual exclusion, and multiple addressing
modes. The architecture supports independent address generation and data
generation/consumption by different processors which increases efficiency and
simplifies programming for many embedded and DSP tasks. Simultaneous access
by different processors is arbitrated using a least-recently-serviced priority scheme.
Simulations show high throughputs over a variety of memory loads. A standard cell
implementation shares an 8 K-word SRAM among four processors,
and can support a 64 K-word SRAM with no additional changes.
It cycles at 555 MHz and occupies 1.2 mm2 in 0.18 μm CMOS.