http://www.hindawi.comThe latest articles from Hindawi Publishing Corporation© 2008, Hindawi Publishing Corporation. All rights reserved.http://www.hindawi.com/GetArticle.aspx?doi=10.1155/2008/171358A novel methodology is presented for the modeling and the simulation of wireless embedded systems. Tight interaction between the analog and the digital functionality makes the design and verification of such systems a real challenge. The applied methodology brings together the functional models of the baseband algorithms written in C language with the circuit descriptions at behavioral level in Verilog or Verilog-AMS for the system simulations in a single kernel environment. The physical layer of an ultrawideband system has been successfully modeled and simulated. The results confirm that this methodology provides a standardized framework in order to efficiently and accurately simulate complex mixed signal applications for embedded systems.Emma Sosa Morales, Giorgia Zucchelli, Martin Barnasconi, and Nitasha Jugessur© 2008, Hindawi Publishing Corporation. All rights reserved.http://www.hindawi.com/GetArticle.aspx?doi=10.1155/2008/519474Functional test generation for dynamic validation of current system level designs is a challenging task. Manual test writing or automated random test generation techniques are often used for such validation practices. However, directing tests to particular reachable states of a SystemC model is often difficult, especially when these models are large and complex. In this work, we present a model-driven methodology for generating directed tests that take the SystemC model under validation to specific reachable states. This allows the validation to uncover very specific scenarios which lead to different corner cases. Our formal modeling is done entirely within the Microsoft SpecExplorer tool to formally describe the specification of the system under validation in the formal notation of AsmL. We also exploit SpecExplorer's abilities for state space exploration for our test generation, and its APIs for connecting the model to real programs to drive the validation of SystemC models with the generated test cases.Hiren D. Patel and Sandeep K. Shukla© 2008, Hindawi Publishing Corporation. All rights reserved.http://www.hindawi.com/GetArticle.aspx?doi=10.1155/2008/726096This paper presents a methodology and techniques for automated integration of dedicated hardwired (HW) IP cores into heterogeneous multiprocessor systems. We propose an IP core integration approach based on an HW module generation that consists of a wrapper around a predefined IP core. This approach has been implemented in a tool called ESPAM for automated multiprocessor system design, programming, and implementation. In order to keep high performance of the integrated IP cores, the structure of the IP core wrapper is devised in a way that adequately represents and efficiently implements the main characteristics of the formal model of computation, namely, Kahn process networks, we use as an underlying programming model in ESPAM. We present details about the structure of the HW module, the supported types of IP cores, and the minimum interfaces these IP cores have to provide in order to allow automated integration in heterogeneous multiprocessor systems generated by ESPAM. The ESPAM design flow, the multiprocessor platforms we consider, and the underlying programming (KPN) model are introduced as well. Furthermore, we present the efficiency of our approach by applying our methodology and ESPAM tool to automatically generate, implement, and program heterogeneous multiprocessor systems that integrate dedicated IP cores and execute real-life applications.Hristo Nikolov, Todor Stefanov, and Ed Deprettere© 2008, Hindawi Publishing Corporation. All rights reserved.http://www.hindawi.com/GetArticle.aspx?doi=10.1155/2008/371768This paper proposes a methodology for modelling and simulation of RF systems in SystemC-WMS. Analog RF modules have been described at system level only by using their specifications. A complete Bluetooth transceiver, consisting of digital and analog blocks, has been modelled and simulated using the proposed design methodology. The developed transceiver modules have been connected to the higher levels of the Bluetooth stack described in SystemC, allowing the analysis of the performance of the Bluetooth protocol at all the different layers of the protocol stack.Simone Orcioni, Mauro Ballicchia, Giorgio Biagetti, Rocco D. d'Aparo, and Massimo Conti© 2008, Hindawi Publishing Corporation. All rights reserved.http://www.hindawi.com/GetArticle.aspx?doi=10.1155/2008/502768Alfons Crespo, Ismael Ripoll, Michael González-Harbour, and Giuseppe Lipari© 2008, Hindawi Publishing Corporation. All rights reserved.http://www.hindawi.com/GetArticle.aspx?doi=10.1155/2008/194697Luca Ferrarini, Jose L. Martinez Lastra, Allan Martel, Antonio Valentini, and Valeriy Vyatkin© 2008, Hindawi Publishing Corporation. All rights reserved.http://www.hindawi.com/GetArticle.aspx?doi=10.1155/2008/731830Toomas P. Plaks, Marco D. Santambrogio, and Donatella Sciuto© 2008, Hindawi Publishing Corporation. All rights reserved.http://www.hindawi.com/GetArticle.aspx?doi=10.1155/2008/250895Achieving end-to-end quality of service (QoS) in distributed real-time embedded (DRE) systems require QoS support and enforcement from their underlying operating platforms that integrates many real-time capabilities, such as QoS-enabled network protocols, real-time operating system scheduling mechanisms and policies, and real-time middleware services. As standards-based quality of service (QoS) enabled component middleware automates integration and configuration activities, it is increasingly being used as a platform for developing open DRE systems that execute in environments where operational conditions, input workload, and resource availability cannot be characterized accurately a priori. Although QoS-enabled component middleware offers many desirable features, however, it historically lacked the ability to allocate resources efficiently and enable the system to adapt to fluctuations in input workload, resource availability, and operating conditions. This paper presents three contributions to research on adaptive resource management for component-based open DRE systems. First, we describe the structure and functionality of the resource allocation and control engine (RACE), which is an open-source adaptive resource management framework built atop standards-based QoS-enabled component middleware. Second, we demonstrate and evaluate the effectiveness of RACE in the context of a representative open DRE system: NASA's magnetospheric multiscale mission system. Third, we present an empirical evaluation of RACE's scalability as the number of nodes and applications in a DRE system grows. Our results show that RACE is a scalable adaptive resource management framework and yields a predictable and high-performance system, even in the face of changing operational conditions and input workload.Nishanth Shankaran, Nilabja Roy, Douglas C. Schmidt, Xenofon D. Koutsoukos, Yingming Chen, and Chenyang Lu© 2008, Hindawi Publishing Corporation. All rights reserved.http://www.hindawi.com/GetArticle.aspx?doi=10.1155/2008/390106We describe a novel and flexible real-time kernel, called Yartek, with low overhead and low footprint suitable for embedded systems. The motivation of this development was due to the difficulty to find a free and stable real-time kernel suitable for our necessities. Yartek has been developed on a Coldfire microcontroller. The real-time periodic tasks are scheduled using nonpreemptive EDF, while the non-real-time tasks are scheduled in background. It uses a deferred interrupt mechanism, and memory is managed using contiguous allocation. Also, a design methodology was devised for the nonpreemptive EDF scheduling, based on the computation of bounds on the periodic task durations. Finally, we describe a case study, namely, an embedded system developed with Yartek for the implementation of nonvisual perception for mobile robots. This application has been designed using the proposed design methodology.Enzo Mumolo, Massimiliano Nolich, and Kristijan Lenac© 2008, Hindawi Publishing Corporation. All rights reserved.http://www.hindawi.com/GetArticle.aspx?doi=10.1155/2008/583926Montgomery's algorithm is a popular technique to speed up modular multiplications in public-key cryptosystems. This paper tackles the efficient support of modular exponentiation on inexpensive circuitry for embedded security services and proposes a variant of the finely integrated product scanning (FIPS) algorithm that is targeted to digital signal processors. The general approach improves on the basic FIPS formulation by removing potential inefficiencies and boosts the exploitation of computing resources. The reformulation of the basic FIPS structure results in a general approach that balances computational efficiency and flexibility. Experimental results on commercial DSP platforms confirm both the method's validity and its effectiveness.P. Gastaldo, G. Parodi, and R. Zunino© 2008, Hindawi Publishing Corporation. All rights reserved.http://www.hindawi.com/GetArticle.aspx?doi=10.1155/2008/369040 With the increased size and complexity of digital designs, the time required to simulate them has also increased. Traditional simulation accelerators utilize FPGAs in a static configuration, but this paper presents an analysis of six register transfer level (RTL) code bases showing that only a subset of the simulation processes is executing at any given time, a quality called executive locality of reference. The efficiency of acceleration hardware can be improved when it is used as a process cache. Run-time adaptations are made to ensure that acceleration resources are not wasted on idle processes, and these adaptations may be affected through process migration between software and hardware. An implementation of an embedded, FPGA-based migration system is described, and empirical data are obtained for use in mathematical and algorithmic modeling of more complex acceleration systems. Aric D. Blumer and Cameron D. Patterson© 2008, Hindawi Publishing Corporation. All rights reserved.http://www.hindawi.com/GetArticle.aspx?doi=10.1155/2008/793919Reconfigurable computing is certainly one of the most important emerging research topics on digital processing architectures over the last few years. The introduction of run-time reconfiguration (RTR) on FPGAs requires appropriate design flows and methodologies to fully exploit this new functionality. For that purpose, we present an automatic design generation methodology for heterogeneous architectures based on DSPs and FPGAs that ease and speed RTR implementation. We focus on how to take into account specificities of partially reconfigurable components from a high-level specification during the design generation steps. This method automatically generates designs for both fixed and partially reconfigurable parts of an FPGA with automatic management of the reconfiguration process. Furthermore, this automatic design generation enables a reconfiguration prefetching technique to minimize reconfiguration latency and buffer-merging techniques to minimize memory requirements of the generated design. This concept has been applied to different wireless access schemes, based on a combination of OFDM and CDMA techniques. This implementation example illustrates the benefits of the proposed design methodology.Florent Berthelot, Fabienne Nouvel, and Dominique Houzet© 2008, Hindawi Publishing Corporation. All rights reserved.http://www.hindawi.com/GetArticle.aspx?doi=10.1155/2008/251957This paper deals with further development of a graphical specification language resembling timing-diagrams and allowing specification of partially ordered events in input and output signals. The language specifically aims at application in modular modelling of industrial automation systems and their formal verification via model-checking. The graphical specifications are translated into a model which is connected with the original model under study.Valeriy Vyatkin and Gustavo Bouzon© 2008, Hindawi Publishing Corporation. All rights reserved.http://www.hindawi.com/GetArticle.aspx?doi=10.1155/2008/259686The research field of system partitioning in modern electronic system design started to find strong advertence of scientists about fifteen years ago. Since a multitude of formulations for the partitioning problem exist, the same multitude could be found in the number of strategies that address this problem. Their feasibility is highly dependent on the platform abstraction and the degree of realism that it features. This work originated from the intention to identify the most mature and powerful approaches for system partitioning in order to integrate them into a consistent design framework for wireless embedded systems. Within this publication, a thorough characterisation of graph properties typical for task graphs in the field of wireless embedded system design has been undertaken and has led to the development of an entirely new approach for the system partitioning problem. The restricted range exhaustive search algorithm is introduced and compared to popular and well-reputed heuristic techniques based on tabu search, genetic algorithm, and the global criticality/local phase algorithm. It proves superior performance for a set of system graphs featuring specific properties found in human-made task graphs, since it exploits their typical characteristics such as locality, sparsity, and their degree of parallelism.B. Knerr, M. Holzer, and M. Rupp© 2008, Hindawi Publishing Corporation. All rights reserved.http://www.hindawi.com/GetArticle.aspx?doi=10.1155/2008/137295A field-programmable-gate-array-(FPGA-) based data acquisition and control system was designed in a hardware/software codesign environment using an embedded Xilinx Microblaze soft-core processor for use with a subsurface ion mobility spectrometer (IMS) system, designed for detection of gaseous volatile organic compounds (VOCs). An FPGA is used to accelerate the digital signal processing algorithms and provide accurate timing and control. An embedded soft-core processor is used to ease development by implementing nontime critical portions of the design in software. The design was successfully implemented using a low-cost, off-the-shelf Xilinx Spartan-III FPGA and supporting digital and analog electronics.Sin Ming Loo, Jonathan P. Cole, and Molly M. Gribb© 2008, Hindawi Publishing Corporation. All rights reserved.http://www.hindawi.com/GetArticle.aspx?doi=10.1155/2008/748652In order to realize autonomous manufacturing systems in environments characterized by high dynamics and high complexity of task, it is necessary to improve the control system modelling and performance. This requires the use of better and reusable abstractions. In this paper, we explore the metamodel techniques as a foundation to the solution of this problem. The increasing popularity of model-driven approaches and a new generation of tools to support metamodel techniques are changing software engineering landscape, boosting the adoption of new methodologies for control application development.Luca Ferrarini, Giuseppe Fogliazza, Giulia Mirandola, and Carlo Veber© 2008, Hindawi Publishing Corporation. All rights reserved.http://www.hindawi.com/GetArticle.aspx?doi=10.1155/2008/426713Formal model of IEC 61499 syntax and its unambiguous execution semantics are important for adoption of this international standard in industry. This paper proposes some elements of such a model. Elements of IEC 61499 architecture are defined in a formal way following set theory notation. Based on this description, formal semantics of IEC 61499 can be defined. An example is shown in this paper for execution of basic function blocks. The paper also provides a solution for flattening hierarchical function block networks.Victor Dubinin and Valeriy Vyatkin© 2008, Hindawi Publishing Corporation. All rights reserved.http://www.hindawi.com/GetArticle.aspx?doi=10.1155/2008/231630A new concept for distributed control systems based on the new IEC 61499 standard is tested in this work in cooperation with LAE Engineering GmbH, a medium-sized company. Based on a catalogue of requirements, a customer-related testbed is developed. In the following this testbed is used as a reference to realise an IEC 61499 compliant-distributed control system based on PC technics. By doing this, rules are defined to convert user-owned IEC 61131 function blocks to IEC 61499 compliant function blocks. Concluding, some trends for IEC 61499-based distributed control systems will be summarised.Christian Gerber, Hans-Michael Hanisch, and Sven Ebbinghaus© 2008, Hindawi Publishing Corporation. All rights reserved.http://www.hindawi.com/GetArticle.aspx?doi=10.1155/2008/267560Peer-to-peer computing principles have started to pervade into mechanical control systems, inducing a paradigm shift from centralized to autonomic control. We have developed a self-contained, miniaturized, universal and scalable peer-to-peer based hardware-software system, the peer-it platform, to serve as a stick-on computer solution to raise real-world artefacts like, for example, machines, tools, or appliances towards technology-rich, autonomous, self-induced, and context-aware peers, operating as spontaneously interacting ensembles. The peer-it platform integrates sensor, actuator, and wireless communication facilities on the hardware level, with an object-oriented, component-based coordination framework at the software level, thus providing a generic platform for sensing, computing, controlling, and communication on a large scale. The physical appearance of a peer-it supports pinning it to real-world artefacts, while at the same time integrating those artefacts into a mobile ad hoc network of peers. Peer-it networks thus represent ensembles of coordinated artefacts, exhibiting features of autonomy like self-management at the node level and self-organization at the network level. We demonstrate how the peer-it system implements the desired flexibility in automated manufacturing systems to react in the case of changes, whether intended or unexpectedly occuring. The peer-it system enables machine flexibility in that it adapts production facilities to produce new types of products, or change the order of operation executed on parts instantaneously. Secondly, it enables routing flexibility, that is, the ability to use multiple machines to spontaneously perform the same operation on one part alternatively (to implement autonomic fault tolerance) or to absorb large-scale changes in volume, capacity, or capability (to implement autonomic scalability).A. Ferscha, M. Hechinger, M. dos Santos Rocha, R. Mayrhofer, A. Zeidler, A. Riener, and M. Franz© 2008, Hindawi Publishing Corporation. All rights reserved.http://www.hindawi.com/GetArticle.aspx?doi=10.1155/2008/234710L4-embedded is a microkernel successfully deployed in mobile devices with soft real-time requirements. It now faces the challenges of tightly integrated systems, in which user interface, multimedia, OS, wireless protocols, and even software-defined radios must run on a single CPU. In this paper we discuss the pros and cons of L4-embedded for real-time systems design, focusing on the issues caused by the extreme speed optimisations it inherited from its general-purpose ancestors. Since these issues can be addressed with a minimal performance loss, we conclude that, overall, the design of real-time systems based on L4-embedded is possible, and facilitated by a number of design features unique to microkernels and the L4 family.Sergio Ruocco© 2008, Hindawi Publishing Corporation. All rights reserved.http://www.hindawi.com/GetArticle.aspx?doi=10.1155/2007/54173Multiple-input multiple-output (MIMO) technology enables higher transmission capacity without additional frequency spectrum and is becoming a part of many wireless system standards. Sphere detection has been introduced in MIMO systems to achieve maximum likelihood (ML) or near-ML estimation with reduced complexity. This paper reviews related work on sphere detector implementations and presents an application-specific instruction set processor (ASIP) implementation of K-best list sphere detector (LSD) using transport triggered architecture (TTA). The implementation is based on using memory and heap data structure for symbol vector sorting. The design space is explored by presenting several variations of the implementation and comparing them with each other in terms of their latencies and hardware complexities. An early proposal for a parallelized architecture with a decoding throughput of approximately 5.3 Mbps is presentedJuho Antikainen, Perttu Salmela, Olli Silvén, Markku Juntti, Jarmo Takala, and Markus Myllylä© 2008, Hindawi Publishing Corporation. All rights reserved.http://www.hindawi.com/GetArticle.aspx?doi=10.1155/2008/582648Multiprocessor systems, especially those based on multicore or multithreaded processors, and new operating system architectures can satisfy the ever increasing computational requirements of embedded systems. ASMP-LINUX is a modified, high responsiveness, open-source hard real-time operating system for multiprocessor systems capable of providing high real-time performance while maintaining the code simple and not impacting on the performances of the rest of the system. Moreover, ASMP-LINUX does not require code changing or application recompiling/relinking. In order to assess the performances of ASMP-LINUX, benchmarks have been performed on several hardware platforms and configurations.Emiliano Betti, Daniel Pierre Bovet, Marco Cesati, and Roberto Gioiosa© 2008, Hindawi Publishing Corporation. All rights reserved.http://www.hindawi.com/GetArticle.aspx?doi=10.1155/2008/518904Multiprocessor systems on chips (MPSoCs) are envisioned as the future of embedded platforms such as game-engines, smart-phones and palmtop computers. One of the main challenge preventing the widespread diffusion of these systems is the efficient mapping of multitask multimedia applications on processing elements. Dynamic solutions based on task migration has been recently explored to perform run-time reallocation of task to maximize performance and optimize energy consumption. Even if task migration can provide high flexibility, its overhead must be carefully evaluated when applied to soft real-time applications. In fact, these applications impose deadlines that may be missed during the migration process. In this paper we first present a middleware infrastructure supporting dynamic task allocation for NUMA architectures. Then we perform an extensive characterization of its impact on multimedia soft real-time applications using a software FM Radio benchmark.Andrea Acquaviva, Andrea Alimonda, Salvatore Carta, and Michele Pittau© 2008, Hindawi Publishing Corporation. All rights reserved.http://www.hindawi.com/GetArticle.aspx?doi=10.1155/2008/285160This paper presents a safe and efficient solution to manage asynchronous configurations of dynamically reconfigurable systems-on-chip. We first define our unified RTOS-based framework for HW/SW task communication and configuration management. Then three issues are discussed and solutions are given: the formalization of configuration space modeling including its different dimensions, the synchronization of configuration that mainly addresses the question of task configuration ordering, and the configuration coherency that solves the way a task accepts a new configuration. Finally, we present the global method and give some implementation figures from a smart camera case study.Yvan Eustache and Jean-Philippe Diguet© 2008, Hindawi Publishing Corporation. All rights reserved.http://www.hindawi.com/GetArticle.aspx?doi=10.1155/2008/856756Reconfigurable system is a promising alternative to deliver both flexibility and performance at the same time. New reconfigurable technologies and technology-dependent tools have been developed, but a complete overview of the whole design flow for run-time reconfigurable systems is missing. In this work, we present a design flow instantiation for such systems using a real-life application. The design flow is roughly divided into two parts: system level and implementation. At system level, our supports for hardware resource estimation and performance evaluation are applied. At implementation level, technology-dependent tools are used to realize the run-time reconfiguration. The design case is part of a WCDMA decoder on a commercially available reconfigurable platform. The results show that using run-time reconfiguration can save over 40% area when compared to a functionally equivalent fixed system and achieve 30 times speedup in processing time when compared to a functionally equivalent pure software design.Yang Qu, Kari Tiensyrjä, Juha-Pekka Soininen, and Jari Nurmi© 2008, Hindawi Publishing Corporation. All rights reserved.http://www.hindawi.com/GetArticle.aspx?doi=10.1155/2008/470856Agent-based technologies in production control systems could facilitate seamless reconfiguration and integration of mechatronic devices/modules into systems. Advances in embedded controllers which are continuously improving computational capabilities allow for software modularization and distribution of decisions. Agent platforms running on embedded controllers could hide the complexity of bootstrap and communication. Therefore, it is important to investigate the messaging performance of the agents whose main motivation is the resource allocation in manufacturing systems (i.e., conveyor system). The tests were implemented using the FIPA-compliant JADE-LEAP agent platform. Agent containers were distributed through networked embedded controllers, and agents were communicating using request and contract-net FIPA interaction protocols. The test scenarios are organized in intercontainer and intracontainer communications. The work shows the messaging performance for the different test scenarios using both interaction protocols.Omar Jehovani López Orozco, Jose Luís Martínez Lastra, José A. Pérez García, and María de los Ángeles Cavia Soto© 2008, Hindawi Publishing Corporation. All rights reserved.http://www.hindawi.com/GetArticle.aspx?doi=10.1155/2008/231940We propose two basic wrapper designs and an enhanced wrapper design for arbitrary digital hardware circuit designs such that they can be enhanced with the capability for dynamic swapping controlled by software. A hardware design with either of the proposed wrappers can thus be swapped out of the partially reconfigurable logic at runtime in some intermediate state of computation and then swapped in when required to continue from that state. The context data is saved to a buffer in the wrapper at interruptible states, and then the wrapper takes care of saving the hardware context to communication memory through a peripheral bus, and later restoring the hardware context after the design is swapped in. The overheads of the hardware standardization and the wrapper in terms of additional reconfigurable logic resources and the time for context switching are small and generally acceptable. With the capability for dynamic swapping, high priority hardware tasks can interrupt low-priority tasks in real-time embedded systems so that the utilization of hardware space per unit time is increased.Chun-Hsian Huang and Pao-Ann Hsiung© 2008, Hindawi Publishing Corporation. All rights reserved.http://www.hindawi.com/GetArticle.aspx?doi=10.1155/2008/562326Flexibility becomes a major concern for the development of multimedia and mobile communication systems, as well as classical high-performance and low-energy consumption constraints. The use of general-purpose processors solves flexibility problems but fails to cope with the increasing demand for energy efficiency. This paper presents the DART architecture based on the functional-level reconfiguration paradigm which allows a significant improvement in energy efficiency. DART is built around a hierarchical interconnection network allowing high flexibility while keeping the power overhead low. To enable specific optimizations, DART supports two modes of reconfiguration. The compilation framework is built using compilation and high-level synthesis techniques. A 3G mobile communication application has been implemented as a proof of concept. The energy distribution within the architecture and the physical implementation are also discussed. Finally, the VLSI design of a 0.13 μm CMOS SoC implementing a specialized DART cluster is presented.Sébastien Pillement, Olivier Sentieys, and Raphaël David© 2008, Hindawi Publishing Corporation. All rights reserved.http://www.hindawi.com/GetArticle.aspx?doi=10.1155/2008/219807The amount of IT devices and services incorporated in the industrial environment has led to the need to design mechanisms that will ensure its correct operation and minimise stoppage times. This paper proposes a system based on service-oriented architectures that allows the correct operation and monitoring of the applications and services running in this type of production elements. The main component of the system is a reduced size network device—that we have named eNSM device—in which the monitoring function proposed has been embedded as a web service. The whole system is based on a distributed application whose components are software agents. In addition, an application protocol named NSMP has been defined for communication between these agents.Francisco Maciá-Pérez, Diego Marcos-Jorquera, and Virgilio Gilart-Iglesias© 2008, Hindawi Publishing Corporation. All rights reserved.http://www.hindawi.com/GetArticle.aspx?doi=10.1155/2008/312671Currently available toolsets for the development of embedded systems adopt traditional architectural styles and do not cover the whole requirements of the development process, with extensibility being the major drawback. In this paper, a service-oriented architectural framework that exploits semantic web is defined. Features required in the development process are defined as web services and published into the public domain, so as to be used on demand by developers to construct their projects' specific integrated development environments (IDEs). The infrastructure required to build a web service-based IDE is presented. Specific web services are defined and the way these services affect the development process is discussed. Special focus is given on the device model and the means that such a modelling can significantly improve the development process. A prototype implementation demonstrates the applicability and usefulness of the proposed demand-led development process in the industrial automation domain.K. C. Thramboulidis, G. Doukas, and G. Koumoutsos© 2008, Hindawi Publishing Corporation. All rights reserved.